Method for forming a strained transistor by stress...

Details Method for forming a strained transistor by stress... Method for forming a strained transistor by stress...

2011-06-21

2011-06-21

Chen, Jack (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S229000, C438S231000, C257SE21476

Reexamination Certificate

active

07964458

ABSTRACT:
By using an implantation mask having a high intrinsic stress, SMT sequences may be provided in which additional lithography steps may be avoided. Consequently, a strain source may be provided without significantly contributing to the overall process complexity.

REFERENCES:
patent: 2003/0151109 (2003-08-01), Taniguchi et al.
patent: 2004/0262784 (2004-12-01), Doris et al.
patent: 2005/0136583 (2005-06-01), Chen et al.
patent: 2005/0199958 (2005-09-01), Chen et al.
patent: 2006/0017138 (2006-01-01), Ting
patent: 2006/0073650 (2006-04-01), Sridhar et al.
patent: 2006/0099745 (2006-05-01), Hsu et al.
patent: 2006/0099765 (2006-05-01), Yang
Ortolland et al., “Stress Memorization Technique (SMT) Optimization for 45nm CMOS,”2006 Symposium on VLSI Technology Digest of Technical Papers, 2006.
PCT Search Report from PCT/US2007/016579 dated Jan. 21, 2008.

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