Method for forming a stacked gate

Details Method for forming a stacked gate Method for forming a stacked gate

1999-04-16

2001-01-09

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000, C438S596000, C438S296000

Reexamination Certificate

active

06171909

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103048, filed Mar. 1, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a flash memory cell, and more particularly, to a method for forming a stacked gate.
2. Description of Related Art
Recently, high-density flash memories have been receiving much attention for application in many fields. One of the most important factors is the low cost of the reduced size of each flash memory cell. However, it is very hard to shrink the cell size in the fabrication of conventional flash memory cells, because a local oxidation (LOCOS) isolation technique is used. The isolation structure formed by the technique limits a reduction of the flash memory.
Another isolation technique called shallow trench isolation (STI) has been disclosed. The fabrication of a flash memory cell comprises the implementation of the STI technique to reduce the cell size. The small-sized cell benefits the integration of the flash memory cell on a wafer. However, the coupling ratio of the cell decreases as the size of the cell becomes small. The decrease is because the overlapping area between the floating gate and the control gate in the cell is reduced.
When the coupling ratio is low, a higher voltage must be supplied in order to operate the memory programming and erasing actions. A high operating voltage makes any dimensional reduction of the flash memory cell very difficult. On the other hand, for a flash memory cell having a high coupling ratio, the electric field necessary to initiate an F-N tunneling is high, thereby slowing the tunneling speed of electrons from the floating gate to the source/drain region. The effect slows down the speed of a read or a write operation in the flash memory.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a method for increasing the coupling ratio of a memory cell.
In another aspect, the present invention provides a method for reducing the size of a memory cell.
In a further aspect, the present invention provides a method for forming a stacked gate of a flash memory cell. A first dielectric layer, a conductive layer and a silicon nitride layer are sequentially formed over a substrate. A photoresist pattern is formed over the silicon nitride layer. The silicon nitride layer, conductive layer, first dielectric layer and substrate are etched with the photoresist pattern serving as an etching mask until a plurality of trenches is formed in the substrate. An insulating layer is formed over the substrate, wherein the insulating layer has a surface level between a top surface of the conductive layer and a bottom surface of the conductive layer. A conductive spacer is formed on the sidewalls of the conductive layer and silicon nitride layer, wherein the conductive spacer and conductive layer serve as a first gate conductive layer. The silicon nitride layer is removed. A second dielectric layer and a second gate conductive layer are formed over the substrate. The second gate conductive layer, second dielectric layer and first gate conductive layer are patterned to form a control gate, a patterned dielectric layer and a floating gate, respectively.
The coupling ratio of the stacked gate comprising the floating gate and control gate is increased by forming the conductive spacer. The size of a memory cell comprising the stacked gate is reduced by patterning the conductive layer and forming the trenches at the same time.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5652161 (1997-07-01), Ahn
patent: 5756384 (1998-05-01), Tseng
patent: 5950090 (1999-09-01), Chen et al.
patent: 5981365 (1999-11-01), Cheek et al.

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