Method for forming a stacked capacitor

Details Method for forming a stacked capacitor Method for forming a stacked capacitor

1999-11-30

2001-03-13

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S253000

Reexamination Certificate

active

06200850

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of manufacturing dynamic random access memory (DRAM), and more particularly to a method for forming a stacked DRAM capacitor.
2. Description of the Related Art
As semiconductor manufacturing advances into the deep submicron range, dimensions of devices shrink considerably. Due to a shorter circuit path, the performance level of an integrated circuit is raised. In general, for the same circuit layout of semiconductor devices, operating speed is related to device density. As density of device increases, space allocated for the construction of DRAM capacitor is reduced. In other words, dimensions of each DRAM capacitor and hence the maximum quantity of electric charges stored inside each capacitor are reduced. Consequently, frequent recharging of the DRAM capacitor is necessary and data processing speed of the DRAM unit is lowered.
Many capacitor structures are developed for increasing surface area of a lower electrode to increase capacitance. In a conventional process of manufacturing a DRAM capacitor, a bit line is formed within a first dielectric layer over a substrate. A second dielectric is formed on the first dielectric layer. An opening is formed through the second dielectric layer and the first dielectric layer to expose a part of the substrate. A conductive material is formed into the opening to form a lower electrode.
FIGS. 1A-1E
are schematic, cross-sectional views showing a conventional method for forming the lower electrode.
Referring to
FIG. 1A
, a substrate
100
having a field oxide
102
is provided. A gate oxide layer
104
is formed on the substrate
100
. A polysilicon layer
106
is formed on the gate oxide layer
104
. A cap layer
108
is formed on the polysilicon layer
106
to protect the polysilicon layer
106
.
In
FIG. 1B
, the cap layer
108
, the polysilicon layer
106
and the gate oxide layer
104
are defined to form a gate structure. The gate structure comprises the gate oxide layer
104
a
, the polysilicon layer
106
a
and the cap layer
108
a
. An ion implantation process is performed to form doped regions
110
within the substrate
100
beside the gate structure.
In
FIG. 1C
, a thin buffer oxide layer
112
is formed over the structure shown in
FIG. 1B. A
silicon nitride spacer
114
is formed on the sidewall of the gate structure. A planarized dielectric layer
116
is formed over the whole substrate
100
. The buffer oxide layer
112
is used to release stress from the silicon nitride spacer
114
.
In
FIG. 1D
, a part of dielectric layer
116
is etched to form a bit line contact opening
118
. Conductive material is formed on the dielectric layer
116
and fills the contact opening
118
. The conductive material is defined to form a bit line
120
electrically connecting to the substrate
100
.
In
FIG. 1E
, a planarized dielectric layer
122
is formed over the structure shown in
FIG. 1D. A
photolithography and etching process is performed to form a node contact opening
124
exposing a part of the doped region
110
. Conductive material
126
is formed to fill the node contact opening
124
and then defined to form a lower electrode of a capacitor.
The conventional method for forming a lower electrode has several disadvantages. One is that the conductive material serving as the bit line
120
may make contact with the polysilicon layer
106
a
of the gate structure. When the dielectric layer
116
is defined to form the bit line contact opening
118
and a misalignment happens, the position of the bit line contact opening
118
covers a portion of the gate structure. The dielectric layer
116
and the buffer oxide layer
112
are made from the same material, silicon oxide. Thus, the buffer oxide layer
112
is etched while etching the dielectric layer
116
to form the bit line contact opening
118
. The polysilicon layer
106
a
is exposed after the buffer oxide layer being etched. As the bit line
120
fills in the contact opening
118
, the conductive layer comes in contact with the exposed polysilicon layer
106
a
. A short between the gate structure and the bit line
120
is thus formed.
Another disadvantage is that the node contact opening
124
is formed through the dielectric layers
122
and
116
. The aspect ratio of the node contact opening
124
is too large. Thus, the etching process for forming the contact opening
124
is difficult to perform and the conductive material used to form the lower electrode
126
also fills the node contact opening
124
with difficulty.
SUMMARY OF THE INVENTION
The invention provides a method for forming a stacked capacitor. A substrate is provided and is defined to form a memory cell region and a peripheral region. Isolation structures are formed on the substrate. A gate oxide layer and a polysilicon layer are formed over the substrate. The polysilicon layer and the gate oxide layer are defined to form a first gate on the memory cell region and to form a second gate on the peripheral region. Ion implantation is performed to form first doped regions in the substrate beside the first and second gates. Spacers are formed on the sidewalls of the first and second gates. A first dielectric layer is formed over the gates and the substrate. A node contact opening and a bit line contact opening are formed within the first dielectric layer to expose the substrate. The bit line contact opening further separates the first gate into two portions. Second doped regions are formed in the substrate exposed by the openings. Spacers are formed on the sidewalls of the openings. Conductive material is formed in the openings to form a bit line and a node landing pad. A second dielectric layer having an opening exposing the landing pad is formed over the first dielectric layer. Conductive material is formed to fill the opening in the second dielectric layer, thereby to form a lower electrode.
The bit line opening is formed by etching the first dielectric layer and the first gate. The opening is then filled with the conductive material. The opening has a spacer on its sidewall, so that the conductive material does not make contact with the polysilicon layer of the gate. Furthermore, the landing pad is formed while forming the bit line. The landing pad is a part of the lower electrode. After forming the second dielectric layer, a via opening is formed within the second dielectric layer to expose the landing pad. The aspect ratio of the via opening is smaller than a conventional node contact opening. Thus, the etching process for forming the via opening is easily performed. The step of forming conductive material in the via opening is also easily performed.


REFERENCES:
patent: 5612241 (1997-03-01), Arima
patent: 5955758 (1999-09-01), Sandhu et al.
patent: 6008084 (1999-12-01), Sung

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