Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-06-22
2003-08-26
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06610573
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electrical circuits on semiconductor substrates, specifically on trench DRAM architecture and more specifically to a process for forming a top oxide on an array of memory cells using vertical transistors whereas the support contains planar transistors.
BACKGROUND OF THE INVENTION
The primary driving motivator in commercial memory cells and architecture is the desire to pack more memory capability into a smaller integrated circuit. This goal necessarily involves competing trade-offs in cost, circuit complexity, power dissipation, yield, performance, and the like. Trench capacitors are known in the art as an architecture whereby the overall size (in terms of surface area or chip “real estate”) of the memory cell is reduced. The size reduction is accomplished by taking a planar capacitor element of the memory cell and forming the capacitor instead in a trench.
As is known in the art, a typical DRAM cell includes a capacitor upon which is stored a charge (or no charge depending upon the cell's state) and a pass transistor, which is used to charge the capacitor during writing and in the read process to pass the charge on the capacitor to a sense amplifier. In current manufacturing, planar transistors are used for the pass transistors and for the support circuits. Such planar transistors have a critical dimension of gate length that cannot be shrunk below approximately 110 nm maintaining the on and off current required for DRAM retention. Below that size, the transistor performance becomes degraded and is very sensitive to process tolerances. As such, for DRAM cells that are desired to be shrunk, vertical transistors have been proposed for the array. See, for instance, Ulrike Gruening et al., IEDM Tech.Dig. p. 25 (1999) and Carl Radens et al., IEDM Tech.Dig. p. 15.1.1 (2000). Vertical transistors require additional processing, however, thus leading to additional overall costs in manufacturing the device.
Furthermore, the unique processing steps required for vertical gate transistors require modified process flows for manufacturing the memory arrays. The process steps involved in forming the vertical array transistors will deviate from the steps involved in forming the “support” transistors (such as the sense amps, wordline decoder and periphery circuits). Because of this, a need exists in the art for a manufacturing process in which both vertical gate array transistors and planar support transistors can be manufactured on the same semiconductor substrate without unnecessary additional process steps that can add to the cost and reduce the manufacturing yield of the resulting chips. A solution that allows the use of the same wiring layer for the vertical transistors gates as is already used for the formation of the gates of the planar transistors would provide further advantage.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides for a method for forming one wiring connection for vertical and planar transistors together in an electrical circuit on a substrate, the substrate having a surface including regions comprising vertical transistors formed therein and other regions comprising planar transistors formed therein. The method includes forming a vertical transistor on a sidewall of a trench formed within the surface, having a vertical gate formed within the trench and extending above surface, growing a planar gate oxide over both the surface and the vertical gate extending above the surface, depositing a conductive layer on the surface, and forming an etch mask on top of the conductive layer. The etch mask exposes the regions comprising vertical transistors formed therein and covers the regions comprising planar transistors formed therein. The method further includes etching the conductive layer in the exposed regions, removing the etch mask, forming a thick oxide layer on the surface, removing the thick oxide layer from the regions comprising planar transistors formed therein and from the vertical gate extending above the surface, and forming a conductor above and contacting the vertical gate extending above the surface, wherein the conductor is insulated from doped regions adjacent the trench by the thick oxide layer.
In another aspect, the invention provides for memory cell array comprising
an array region and a support region. The array region comprises an active trench having a gate polysilicon layer formed therein and having a gate oxide formed on a sidewall thereof, the gate polysilicon having a stud protruding above bulk silicon surrounding said trench. The array region further comprises a doped region formed within bulk silicon adjacent the trench and an oxide layer formed over the bulk silicon adjacent the trench. The support region comprises a planar transistor having a first and second doped region formed within bulk silicon, and having a gate oxide formed above the bulk silicon adjacent the first and second doped regions and a polysilicon layer formed above the gate oxide. The memory cell array further comprises an isolation trench adjacent the active trench. The oxide layer overlies a portion of the isolation trench and the polysilicon overlies a portion of the isolation trench and is adjacent the oxide layer.
The preferred embodiments of the present invention provide the advantage of manufacturing simplicity in that the number of masks and photolithographic steps in forming both planar devices and vertical devices in a single substrate is minimized.
The preferred embodiments provide the further advantage that the conductors and nitride cap of the finished devices are substantially planar, thus simplifying subsequent processing steps.
Additionally, because the thick oxide layer is applied late in the process, it can be used to insulate the vertical gate from surrounding active regions, thus minimizing mis-alignment tolerance.
REFERENCES:
patent: 5627092 (1997-05-01), Alsmeier et al.
patent: 6143635 (2000-11-01), Boyd et al.
patent: 6172390 (2001-01-01), Rupp et al.
patent: 6190971 (2001-02-01), Gruening et al.
patent: 6200851 (2001-03-01), Arnold
patent: 0 977 256 (2000-02-01), None
Gruening, et al., “A Novel Trench DRAM Cell with aVERtIcal Access Transistor andBuriEdSTrap (VERI BEST) for 4Gb/16Gb”, IEEE, 1999.
Radens, et al., “An Orthogonal 6F2Trench-Sidewall Vertical Device Cell for 4Gb/16Gb DRAM”, 2000. (Abstract Only).
Coleman William David
Infineon - Technologies AG
Slater & Matsil L.L.P.
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