Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-11-07
2006-11-07
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S242000, C438S258000, C257SE51005, C257SE29137
Reexamination Certificate
active
07132322
ABSTRACT:
Form a dielectric layer on a semiconductor substrate. Deposit an amorphous Si film or a poly-Si film on the dielectric layer. Then deposit a SiGe amorphous-Ge or polysilicon-Ge thin film theteover. Pattern and etch the SiGe film using a selective etch leaving the SiGe thin film intact in a PFET region and removing the SiGe film exposing the top surface of the Si film in an NFET region. Anneal to drive Ge into the Si film in the PFET region. Deposit a gate electrode layer covering the SiGe film in the PFET region and cover the exposed portion of the Si film in the NFET region. Pattern and etch the gate electrode layer to form gates. Form FET devices with sidewall spacers and source regions and drains regions in the substrate aligned with the gates.
REFERENCES:
patent: 6150205 (2000-11-01), Chen et al.
patent: 6248618 (2001-06-01), Quek et al.
patent: 6524902 (2003-02-01), Rhee et al.
patent: 6709912 (2004-03-01), Ang et al.
patent: 6730588 (2004-05-01), Schinella
patent: 2003/0203554 (2003-10-01), Kubo et al.
patent: 2004/0067631 (2004-04-01), Bu et al.
patent: 2004/0217430 (2004-11-01), Chu
E.J. Stewart, M.S. Carroll, and James C. Sturm entitled “suppression of Boron Penetration in P-Channel MOSFETS Using Polycrystalline Si l-x-y GexCy Gate Layers” in IEEE Electron Device Letters, vol. 22, No. 12 (Dec. 2001) pp. 574-576.
E.J. Stewart, M.S. Carroll, and James C. Sturm entitled “Boron Segregation adn Electrical Properties in Polycrystalline Si l-x-y Gex Cy and Sil-yCy Layers” in JOurnal of applied Physics, vol. 95 No. 8 (Apr. 15, 2004) pp. 4029-4035.
Greene Brian Joseph
Rim Kern
Wann Clement
Jones II Graham S.
Lebentritt Michael
Schnurmann H. Daniel
Ullah Elias
LandOfFree
Method for forming a SiGe or SiGeC gate selectively in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a SiGe or SiGeC gate selectively in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a SiGe or SiGeC gate selectively in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3659492