Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-12-18
2001-11-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S404000, C438S424000
Reexamination Certificate
active
06323092
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application Ser. No. 87121256, filed Dec. 19, 1998.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for forming a shallow trench isolation (STI) of a semiconductor device.
2. Description of the Relation Art
An isolation region is formed in an integrated circuit for preventing a short circuit from occurring between adjacent device regions on a substrate. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions on semiconductor device. However, since internal stress is generated and bird's beak encroachment occurs in the isolation structures, LOCOS cannot effectively isolate devices.
The shallow trench isolation (STI) technique has been developed to improve the bird's beak encroachment of the LOCOS so as to achieve an effective isolation structure. Typically, the STI process comprises the steps of using a mask to define and pattern a shallow trench on a substrate by anisotropic etching process, and then filling he shallow trench with oxide for use as a device isolation structure.
FIGS. 1A through 1E
are schematic, cross-sectional views showing the progression of the conventional manufacturing steps for a shallow trench isolation structure. Referring to
FIG. 1A
, a pad oxide layer
102
is formed by thermal oxidation on a substrate
100
. The pad oxide layer
102
is used to protect the substrate
100
surface during the whole processes. A silicon nitride layer
104
as a mask layer is formed by low pressure chemical vapor deposition (LPCVD) on the pad oxide layer
102
.
Referring to
FIG. 1B
, a photoresist layer is formed on the silicon nitride layer
104
, after which a portion of the silicon nitride layer
104
, the pad oxide layer
102
and the substrate
100
are removed by etching to form a trench
112
within the substrate
100
and expose the substrate
100
. Then, the photoresist layer is removed from the silicon nitride layer
104
.
Referring to
FIG. 1C
, a liner layer
114
is formed by high temperature thermal oxidation on the trench
112
surface. The liner layer
114
extends to a top corner
140
of the trench
112
and connects with the pad oxide layer
102
. An insulation layer
116
is deposited by atmospheric pressure chemical vapor deposition (APCVD) with tetra-ethyl-ortho-silicate (TEOS) as a gas source over the silicon nitride layer
104
and within the trench
112
. The insulation layer
116
is made of silicon oxide. A densification step is subsequently performed on the insulation layer
116
at high temperature.
Referring to
FIG. 1D
, the silicon nitride layer
104
is used as a polishing stop layer, and a portion of the insulation layer
116
above the surface of the silicon nitride layer
104
is removed by chemical mechanical polishing (CMP) to form an insulation layer
116
a
and expose the silicon nitride layer
104
. A surface of the insulation layer
116
a
surface is level with a surface of the silicon nitride layer
104
.
Referring to
FIG. 1E
, the silicon nitride layer
104
is removed by using a hot phosphoric acid (H
3
PO
4
) to expose the pad oxide layer
102
. The pad oxide layer
102
is removed by using hydrogen fluoride (HF) to form a shallow trench isolation structure
117
.
The pad oxide layer
102
is removed by isotropic etching, using hydrogen fluoride (HF); however, the isotropic etching has a tendency to etch laterally. After performing the isotropic etching process, a recess
150
occurs, in the top corner
140
(
FIG. 1C
) of the trench
112
because insulation layer
116
a
covers the top corner
140
of the trench
112
. The recess
105
leads to a kink effect, and the kink effect causes a threshold voltage reduction and leads to generation of a leakage current while forming the corner parasitic MOSFET.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide an improved method for forming a shallow trench isolation structure. The method can prevent recess generation and avoid the kink effect induced in the top corner of the shallow trench.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for forming a shallow trench isolation structure. A substrate having a pad oxide layer and a first mask layer is provided. The first mask layer is patterned to form a first opening and a spacer is formed on the first mask layer sidewalls. The patterned first mask layer and the spacer are used as a hard mask and a portion of the pad oxide layer and the substrate are removed to form a shallow trench within the substrate. A liner layer is formed on the shallow trench surface. An insulation layer is deposited over the patterned first mask layer and within the shallow trench. Using the patterned first mask layer as a stop layer, a portion of the insulation layer above the patterned first mask layer surface is removed. Then, the patterned first mask layer and the spacer are removed. A patterned second mask layer having a second opening is formed on the substrate to expose the insulation layer and a portion of the pad oxide layer. The patterned second mask layer is used as a hard mask to remove the portion of the pad oxide layer, and then an oxide layer is formed by a thermal oxidation process on the substrate. The second patterned mask layer and the pad oxide layer are removed, and then an isolation structure according to this invention is complete.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5904538 (1999-05-01), Son et al.
patent: 6107159 (2000-08-01), Chuang
patent: 6114217 (2000-09-01), Park
patent: 6150072 (2000-11-01), Shoda et al.
Jones Josetta
Niebling John F.
United Microelectronics Corp.
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