Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-07
2001-09-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S303000, C438S591000
Reexamination Certificate
active
06287916
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor processing methods, and more particularly, it relates to a method for manufacturing a non-volatile semiconductor device having a PECVD nitride cap layer which includes a LPCVD barrier layer formed under the cap layer and over the floating gate so as to protect the floating gate from charge loss.
2. Description of the Prior Art
In view of the trend in the semiconductor industry for achieving higher and higher packing densities in integrated circuits, multilayer interconnects are being used to connect the electrical components on two different levels. Typically, a PECVD nitride cap layer is formed underneath a BPTEOS layer which is used as an interlayer dielectric (ILD) between the two different levels. Unfortunately, the PECVD nitride cap layer has a high hydrogen ion content. As is generally known, one of the major concerns in the fabrication of non-volatile memory devices is that of high temperature data retention which is believed to be caused by mobile hydrogen ions. These mobile ions can diffuse to the floating gate in the non-volatile memory devices and cause charge loss.
Traditionally, the prior art semiconductor processing for non-volatile memory devices having a PECVD nitride cap layer formed underneath the BPTEOS oxide films utilized a phosphorus implant into the cap layer followed by a high temperature heat treatment (e.g., RTA) at about 800° C. for removing of the free hydrogen ions. Further, a hydrogen getter layer may be formed over the floating gate so as to order to getter mobile ions that may be present in the semiconductor device and thus obtain good data retention. For a complete discussion of this prior art technique, reference is made to U.S. Pat. No. 5,940,735 issued on Aug. 17,1999 and entitled “Reduction of Charge Loss in Nonvolatile Memory Cells by Phosphorus Implantation into PECVD Nitride/Oxynitride Films” which is hereby incorporated in its entirety by reference.
Accordingly, there has arisen a need for a method for manufacturing a non-volatile memory device having a PECVD nitride cap layer which eliminates the phosphorus implant followed the high temperature RTA process, but yet protect the floating gate from charge loss. This is achieved in the present invention by forming a LPCVD nitride film under the PECVD nitride cap layer and over the floating gate so as to protect the floating gate from charge loss.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS film which overcomes the problems of the prior art methods.
It is an object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS film which eliminates the phosphorus implant followed by a high temperature RTA process, but yet protect the floating gate from charge loss.
It is another object of the present invention to provide an improved method for fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS film which includes a LPCVD nitride barrier layer disposed between the cap layer and the floating gate.
It is still another object to provide an improved method for fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS film which includes the step of performing a low pressure chemical vapor deposition nitride film at a temperature of about 700 to 800° C. after the formation of the floating gate so as to protect the same from charge loss.
In accordance with a preferred embodiment of the present invention, there is provided an improved method of fabricating a non-volatile semiconductor device having a PECVD nitride cap layer formed under a BPTEOS oxide film. The present method utilizes the step of forming a layer of LPCVD nitride film over the floating gate so as to prevent charge loss. A PECVD nitride cap layer is deposited on top of the layer of LPCVD nitride film over the entire surface of the semiconductor device. A BPTEOS oxide film is deposited on top of the PECVD nitride cap layer over the entire surface of the semiconductor device. A RTA step at a temperature of about 800° C. is performed immediately after the deposition of the BPTEOS film so as to densify and stabilize the same. Then, a CMP step is performed so as to planarize the BPTEOS film.
REFERENCES:
patent: 5885858 (1999-03-01), Nishimura et al.
patent: 5940735 (1999-08-01), Mehta et al.
patent: 6037223 (2000-03-01), Su et al.
patent: 6060766 (2000-05-01), Mehta et al.
patent: 6071784 (2000-06-01), Mehta et al.
Bowers Charles
Chen Jack
Chin Davis
Lattice Semiconductor Corporation
LandOfFree
Method for forming a semiconductor device using LPCVD... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a semiconductor device using LPCVD..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a semiconductor device using LPCVD... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2462500