Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-04-28
2004-10-12
Fahmy, Wael (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S306000, C438S307000, C438S558000
Reexamination Certificate
active
06803287
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device which has a contact wire in connection with the construction of a diffusion layer area, and a method of manufacturing the same which can form the contact wire in connection with the construction of the diffusion layer area without requiring any additional lithographic process.
2. Description of the Related Art
There has been hitherto known so-called asymmetric type transistor in which the impurity concentration of a diffusion layer area is varied between a source area and a drain area in order to enhance the characteristics of the transistor, for example.
FIGS. 3A
to
3
D show the construction of a conventional asymmetric transistor and a method of manufacturing the same.
According to the manufacturing method, as shown in
FIG. 3A
, a silicon oxide film
102
of 100 Å is formed on the surface of a p-type silicon substrate
101
, and then a polycrystal silicon film doped with phosphor is formed at a thickness of 1500 Å, for example. Thereafter, the polycrystal silicon film thus formed is subjected to a patterning treatment to obtain a desired pattern, and it is used as a gate electrode
103
.
Thereafter, for example, a silicon oxide film of 1500 Å is formed and subjected to an anisotropic etch-back treatment to form a side wall
104
on the side surface of the gate electrode
103
. Here, n-type impurities (for example, As) are doped by ion implantation to form a diffusion layer
105
as shown in FIG.
3
B.
Further, as shown in
FIG. 3C
, n-type impurities (for example, As) are additionally doped into only one of the source and the drain by the ion implantation using a lithographic technique to form a diffusion layer
106
having a larger concentration. Reference numeral
107
′ denotes a patterned photoresist film. Thereafter, formation of an insulating film
107
, formation of a contact wire
108
and then formation of a wire
109
are carried out in this order, thereby completing a semiconductor transistor as shown in FIG.
3
D.
As shown in
FIG. 3D
, the structure of the conventional transistor thus formed is designed so that the concentration of the impurities is different between the source and the drain and the contact wires to be connected to the wires provided to the source and the drain are designed to have the same size at both the source side and the drain side.
Accordingly, even when a semiconductor device is designed so that the impurity concentration of a diffusion layer is different from that of another diffusion layer, this design does not greatly contribute to the improvement of the electrical characteristics of the semiconductor device as long as the contact wires to be connected to these diffusion layers are equal in size, thickness or the like.
For example, it is considered that the voltage between the source and the gate of a transistor is prevented from being reduced by setting the impurity concentration of the source area to be larger than that of the drain area. In order to satisfy this structure, it is necessary to reduce the resistance of a contact wire to be connected to the source diffusion layer concerned, and thus it is also necessary to increase the sectional area of the contact wire concerned.
Further, in order to form diffusion layers which are different in impurity concentration, a further lithographic step is required to be added, and thus the number of manufacturing steps is increased, resulting in rise-up of the cost.
Besides, each of JP-60-776(A) and JP-8-18052(A) disclose a method of manufacturing a semiconductor device in which the impurity concentration is set to be asymmetrical between a source diffusion layer area and a drain diffusion layer area, and JP-8-264561(A) discloses a transistor in which P-type impurities and N-type impurities are doped in each of the source and drain diffusion layer areas and which is designed in an asymmetrical structure. However, these prior art publications never disclose a technique of designing a semiconductor device so that the impurity concentration is set to be asymmetrical between both the diffusion layers and also the contact wires to be connected to both the diffusion layers are asymmetrical in sectional area.
Further, JP-11-195787(A) discloses a transistor in which the source diffusion layer area and the drain diffusion layer area are designed to be structurally asymmetrical with respect to the gate electrode, and the shape of the contact wire to be connected to one diffusion layer area is set to be different from that of the contact wire to be connected to the other diffusion layer area. However, it never disclose a technique of designing a transistor that the impurity concentration is set to be asymmetrical between both the diffusion layers and also the contact wires to be connected to both the diffusion layers are set to be asymmetrical in sectional area.
Still further, JP-2,763,025 corresponding to JP-9-283536(A) discloses a transistor in which the source diffusion layer area and the drain diffusion layer area are designed to be structurally asymmetrical with respect to the gate electrode. However, it never disclose a technique of designing a transistor so that the impurity concentration is set to be asymmetrical between both the diffusion layers and also the contact wires to be connected to both the diffusion layers are set to be asymmetrical in sectional area.
SUMMARY OF THE INVENTION
Therefore, the present invention has been implemented to solve the above problems of the prior arts, and has an object to provide a semiconductor device and a semiconductor device manufacturing method which do not need any additional lithographic step and can suppress increase of the manufacturing cost in a process of forming a semiconductor device designed so that the impurity concentration of some of plural diffusion layer areas provided on a semiconductor substrate is set to be different from that of the other diffusion layer areas, or a semiconductor device designed so that the electrical conduction type of some of plural diffusion layer areas provided on a semiconductor substrate is set to be different from that of the other diffusion layer areas.
In order to attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device in which the impurity concentration of at least one of plural diffusion layer areas formed in the semiconductor device is set to be higher than that of the other of diffusion layer areas, and a first contact wire connected to the at least one of diffusion layer areas having the higher impurity concentration is set to be larger in sectional area than a second contact wire connected to the other of diffusion layer areas having the lower impurity concentration.
According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device which comprises the steps of: doping first impurities having a first conduction type into plural predetermined positions in the neighborhood of the surface of a semiconductor substrate or a semiconductor layer to form plural second diffusion layer areas; forming contact wires on the second diffusion layer areas so that a contact wire formed in at least one of the second diffusion layer areas is set to be larger in sectional area than a contact wire formed in the other of the second diffusion layer areas; forming a space portion in the contact wire having the larger sectional area; and further doping first impurities having the same conduction type as the first conduction type into the at least one of the second diffusion layer areas through the space portion with the peripheral edge portion of the contact wire being used as a mask to form a first diffusion layer area having an impurity concentration higher than the impurity concentration of the other of the second diffusion layer areas.
Further, according to a third aspect o
Fahmy Wael
NEC Corporation
Pham Hoai
Young & Thompson
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