Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-29
2003-02-11
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S210000, C438S230000, C438S241000, C438S279000, C438S587000, C438S592000
Reexamination Certificate
active
06518130
ABSTRACT:
BACKGROUND OF THE INVENTION AND RELATED ART STATEMENT
The present invention relates to a semiconductor device and a method of producing the same.
For achieving a decrease in power consumption of transistors constituting a logic circuit (also called a peripheral circuit) and an increase in the speed thereof, it has come to be standard practice to apply a salicide (self-aligned silicide) technology and a dual gate (also called dual work function gate or surface channel type CMOSFET) technology. Further, a semiconductor device having logic circuits and dynamic random access memories (DRAM) mounted together has come to be generally used.
The above salicide technology refers to the technology of forming a silicide layer, in source/drain regions and a top surface of a gate electrode, in a self-aligned manner. In this technology, specifically, the gate electrode composed of polysilicon is formed on a semiconductor substrate, then, the source/drain regions are formed in the semiconductor substrate, then, a metal layer is formed on the entire surface, and heat treatment is carried out to allow atoms constituting the metal layer and atoms (specifically Si) constituting the semiconductor substrate and the gate electrode to react, whereby a silicide layer is formed, followed by the removal of the unreacted metal layer.
The above dual gate technology refers to the technology of forming a gate electrode for an n-channel type MOSFET from a polysilicon layer containing an n-type impurity and forming a gate electrode for a p-channel type MOSFET from a polysilicon layer containing a p-type impurity to form a surface channel in each MOSFET.
The semiconductor device is becoming finer in size, and when a contact plug is formed on a source/drain region of a semiconductor device, generally, there is therefore employed technology of forming the contact plug in a self-aligned manner. Such a technology is called “self-align-contact (SAC) technology”. For applying the SAC technology, the gate electrode is required to have a two-layered structure formed of a polysilicon layer and an offset layer such as a silicon nitride (SiN) layer. For securing the distance between the gate electrode and the contact plug, further, it is required to form gate sidewalls composed of silicon nitride (SiN) on the side walls of the gate electrode.
However, it is said that the compatibility of the fast logic circuit production process including the salicide technology and the dual gate technology and the general DRAM production process is not so well for the following reasons.
[{circle around (1)} DRAM Memory Cell Characteristics]
For securing excellent characteristics of DRAM memory cells, it is preferred not to form a silicide layer on source/drain regions of a transistor constituting a memory element of the DRAM (to be sometimes referred to as “DRAM-constituting transistor” for the convenience hereinafter) for the following reason. That is, due to a leak current caused by a junction which takes place between the source/drain region on a node side and the silicide layer, the data-retention characteristic is deteriorated. Generally, 256 memory elements are connected to one bit line in DRAM of 0.25 &mgr;m generation, and 512 memory elements are connected to one bit line in DRAM of 0.18 &mgr;m generation. Due to an increase in a leak current as a total sum of leak currents caused by junctions between the source/drain regions on a bit line side and the silicide layers, a margin of a low-voltage driving lowers or decreases because of a decrease in the amplitude of a signal flowing in the bit line, and the data-retaining characteristic (for example, refresh characteristic) deteriorates. In the transistor constituting the logic circuit, it is required to improve the source/drain regions in performance by decreasing the resistance thereof, and for this purpose, it is required to form the silicide layers in the source/drain regions.
[{circle around (2)} SAC Technology of DRAM-constituting Transistor]
When the SAC technology is applied to DRAM-constituting transistors, and if a space between the gate electrodes of the transistors is fully filled with a silicon nitride layer, it is inevitable to increase the thickness of the offset layer for making an opening portion in the above silicon nitride layer while reliably securing a process margin. However, when the thickness of the offset layer is increased, a step height difference caused by the gate electrode increases, and disadvantages are liable to occur in steps to follow. Specifically, for example, a margin in a lithography step is liable to decrease, and filling of an insulating interlayer is liable to be defective.
Moreover, when silicon nitride having a relative dielectric constant approximately twice as large as that of silicon oxide is used as a gate sidewall, a fringe capacitance which is a capacitance between the edge portion of the gate electrode and the source/drain region increases, and the fast operation characteristic of the transistor constituting the logic circuit may be affected in some cases.
[{circle around (3)} Space Between Gate Electrodes of DRAM-constituting Transistors]
The distance between the gate electrodes of DRAM-constituting transistors is smaller than the distance between the gate electrodes of transistors constituting the logic circuit. In some cell design, therefore, the width (thickness) of the gate sidewall is determined by optimizing the capability of the transistors constituting the logic circuit, and when such a gate sidewall is formed on the side wall of the gate electrode, a silicon nitride film constituting the gate sidewall may fill a space between the gate electrodes of the DRAM-constituting transistors. Further, if a silicon nitride film is formed as an etching stop layer when a contact plug is formed on the source/drain region of the transistor constituting the logic circuit, the possibility of the silicon nitride film fully filling the space between the gate electrodes of the DRAM-constituting transistors comes to be higher. If the silicon nitride film fully fills the space between the gate electrodes of the DRAM-constituting transistors, it is very difficult to form a contact plug on the source/drain region of the DRAM-constituting transistor according to the SAC technology.
[{circle around (4)} Offset Layer]
When the gate electrode is formed to have the two-layer structure of the polysilicon layer and the offset layer, no silicide layer can be formed on the top surface of the gate electrode due to the presence of the offset layer. Further, when the dual gate technology is applied to the transistor constituting the logic circuit, the conventional process requires the steps of introducing an n-type impurity and a p-type impurity into the polysilicon layer, respectively, then, forming the offset layer, and then, patterning the offset layer and the polysilicon layer. Since, however, the polysilicon layer containing an n-type impurity and the polysilicon layer containing a p-type impurity have different etching rates, it is difficult to simultaneously form the gate electrode having a desired form for an n-channel type MOSFET and the gate electrode having a desired form for a p-channel type MOSFET. Further, the gate insulating layer keeps on decreasing in thickness, so that a semiconductor substrate may be damaged when etching is carried out for forming the gate electrode.
When the offset layer is made from silicon nitride, the step of forming the contact plug on the gate electrode, an extending portion of the gate electrode or a word line inevitably differs from the step of forming the contact plug on the source/drain region, so that additional steps of exposure and etching are required.
OBJECT AND SUMMARY OF THE INVENTION
It is therefore a first object of the present invention to provide a semiconductor device which can overcome the problems described in the above [{circle around (1)} DRAM memory cell characteristics].
It is a second object of the present invention to provide a semiconductor
Chen Jack
Nguyen Tuan H.
Rader & Fishman & Grauer, PLLC
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