Method for forming a semiconductor device

Details Method for forming a semiconductor device Method for forming a semiconductor device

1999-11-22

2001-05-22

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S593000, C438S594000

Reexamination Certificate

active

06235621

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device by using self-align contact (SAC).
2. Description of the Prior Art
With the advent of Ultra Large Scale Integrated (ULSI) semiconductor devices, the size of the semiconductor device becomes smaller and smaller such that the width of a single semiconductor device has become very small. The manufacture of a semiconductor device usually includes the fabrication of the transistor, the bit line, and the word line, and further includes the contacts. The devices of small area in the semiconductor device with self align contact technology are thus very important for the designer.
The traditional technology employed to fabricate the semiconductor device with the polycide gate using self-align contact often suffers from the rough side-wall after LDD oxidation mainly due to the extruded oxides of polycide. This phenomenon mentioned above frequently results in rough and extruding side-wall which degrades the isolation between polycide gates and self-align contacts.
Taking the method for fabricating a semiconductor device, such as a word line or a transistor, as an example, the transistor-manufacturing method is illustrated as prior art. When the substrate
10
is provided in the manufacturing process, the gate oxide layer
11
, the polycrystalline silicon layer
12
, and the tungsten silicide layer
13
are subsequently formed on the substrate
10
. Next, a TEOS oxide layer
14
is optionally formed on the tungsten silicide layer
13
. The TEOS oxide layer
14
can be formed by the CVD (Chemical Vapor Deposition) method. The silicon nitride layer
15
is formed on the TEOS oxide layer
14
, and then the photoresist layer
16
is used as a mask when anisotropically etching the silicon nitride layer
15
and the TEOS oxide layer
14
. Next, referring to
FIG. 1B
, photoresist layer
16
is stripped and the polycrystalline silicon layer
12
and the tungsten silicide layer
13
are anisotropically etched to form the multi-layer. The multi-layer above includes the etched polycrystalline silicon layer
12
, the etched tungsten silicide layer
13
, the etched TEOS oxide layer
14
, and the etched silicon nitride layer
15
.
Referring to
FIG. 1C
, the spacer
20
is formed on the side-wall of the foregoing multi-layer to finish the semiconductor device. However, during the subsequent processes, the oxidation process and the self-align technology are employed to proceed with the semiconductor device. The dielectric layer
25
, such as an oxide layer, referring to
FIG. 1D
, formed on the semiconductor device is then etched to form a contact hole. A portion of the substrate
10
is exposed, and then a conductive layer
30
is formed and patterned on the exposed portion of the spacer
20
and the exposed portion of the gate oxide layer
11
. The dielectric layer
25
and the subsequent processes are performed to manufacture the semiconductor device.
When the oxidation process is applied to the semiconductor device mentioned above, the polycrystalline silicon generated from the side-wall of the tungsten silicide layer
13
will result in a rough and extruded side-wall which degrades the isolation between polycide gates and self-align contacts. The phenomenon mentioned above results from the portion
35
of the thickness reduced spacer
20
.
SUMMARY OF THE INVENTION
Due to the issues mentioned above, it is important to prevent the reduction of isolation margin resulting from the polycide generated on the side-wall of the multi-layer in the subsequent oxidation process. The present invention proposes a simple and practical method of fabricating the semiconductor device utilizing self-align technology, which can increase the isolation margin between the polycide gate and the self-align contact. A method for fabricating semiconductor device is disclosed herein.
The first step is to form a first oxide layer on a substrate. Then subsequently form a polycrystalline silicon layer, a polycide layer, optionally a second oxide layer, and a silicon nitride layer on the first oxide layer. A photoresist pattern is formed on the silicon layer, and the silicon nitride layer is etched using the photoresist pattern as a mask to expose a portion of the polycide layer. Followed by stripping the photoresist pattern, the polycide layer is isotropically etched to form an under cut in the polycide layer under the etched nitride layer (optionally a second oxide layer).
The width of the top portion of the isotropically etched polycide layer is smaller than the width of the etched nitride layer. Subsequently, the isotropically etched polycide layer is anistropically and the polycrystalline layer is etched until a portion of the first oxide layer is exposed to a multi-layer structure. Finally, form spacers are formed on side-walls of the multi-layer structure to form the semiconductor device, the side-wall of the anisotropicaly etched polycide layer generated after the oxidation process is prevented from penetrating the spacer of the semiconductor device according to the present invention.


REFERENCES:
patent: 5698072 (1997-12-01), Fukuda
patent: 5880035 (1999-03-01), Fukuda
patent: 5994237 (1999-11-01), Becker et al.
patent: 5998290 (1999-12-01), Wu et al.

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