Method for forming a semiconductor device

Details Method for forming a semiconductor device Method for forming a semiconductor device

1999-07-21

2001-01-09

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S195000, C438S197000, C438S585000

Reexamination Certificate

active

06171910

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods for forming semiconductor devices and more particularly to methods for forming semiconductor devices including gate electrodes.
BACKGROUND OF THE INVENTION
In semiconductor device fabrication, polysilicon and silicon dioxide are commonly used to form gate electrodes and gate dielectrics for metal-oxide-semiconductor (MOS) transistors. However, the scaling of semiconductor devices into the 0.1 micron (&mgr;m) regime will likely result in problems that will require fabricating gate electrodes and gate dielectrics using alternative materials.
Polysilicon requires the addition of impurities to affect its conductivity. As the transistor is scaled to smaller dimensions, the transistor's resistivity is increased and gate depletion effects can become a factor. Increasing the impurity concentration within the polysilicon to reduce the resistance and the gate depletion effects can contribute to boron penetration effects, which can adversely affect the transistor's performance. In addition, scaling may also necessitate using alternative dielectric materials, such as metal oxides that have dielectric constants greater than that of conventional silicon dioxide in order to reduce tunneling leakage between the gate electrode and the transistor's channel region. Incompatibility issues can exist when using polysilicon gates in conjunction with some metal oxides. The polysilicon can react with the metal oxide and contaminate it, thereby negatively affecting its dielectric constant properties.
Metals are an alternative material currently being investigated to replace polysilicon for use as gate electrodes. Metals offer potential advantages over polysilicon because of their low sheet resistance. However, merging metal gate technology into complementary MOS (CMOS) designs introduces new process integration and manufacturing issues. For example, current polysilicon gate CMOS processes can use a combination of doped N
+
and P
+
polysilicon in respective NMOS and PMOS devices to overcome problems associated with adjusting channel threshold voltages (VT). Metals, however, are not readily doped. Therefore, when replacing polysilicon with metal, efforts have focused on selecting those metals having work functions that are close to the mid band-gap of silicon. This allows the VT of the respective n-channel and p-channel devices to be symmetrical. Unfortunately, these mid-gap metal materials can result in transistor VTs that are not optimized for low-voltage, low-power, high-performance devices.


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