Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2007-10-09
2007-10-09
Smoot, Stephen W. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S595000, C257SE21024
Reexamination Certificate
active
11002586
ABSTRACT:
A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
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Sugihara K. et al: “Parasitic Resistance Reduction in Deep Submicron Dual-Gate Transistors With Partially Elevated Source-Drain Extension Regions Fabricated by Complementary Metal-Oxide-Semiconductor Technologies” Japanese Journal of Applied Physics, Japan Society of Applied Physics. Tokyo, JP, vol. 39, No. 2A, Part 1, Feb. 2000, pp. 387-389, XP001052342, ISSN: D021-4922.
Bonser Douglas
Dakshina-Murthy Srikanteswara
Kelling Mark C.
Nomura Asuka
Advanced Micro Devices , Inc.
McDermott & Will & Emery
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