Method for forming a self aligned contact in a semiconductor...

Details Method for forming a self aligned contact in a semiconductor... Method for forming a self aligned contact in a semiconductor...

1999-06-17

2002-01-08

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S595000, C438S652000, C438S655000, C438S787000

Reexamination Certificate

active

06337275

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a contact pad in a semiconductor device and to a method for forming thereof and, more particularly, to a self aligned contact pad and to a method for forming thereof.
2. Description of Related Art
The advance of semiconductor fabricating techniques has now evolved into the gigabit DRAM era. Recently, with the advance of semiconductor fabrication techniques, a trend toward smaller design rules for semiconductor devices such as gigabit DRAMs has proceeded to the extent that the alignment margin can hardly be secured when aligning a contact plug with a semiconductor layer or interconnect layer underlying the contact plug. Accordingly, to manufacture a gigabit DRAM with a critical dimension of 0.18 micrometer or less, a process is employed which permits the contact plug to be formed by self alignment with a semiconductor layer or interconnect layer underlying the contact plug.
The advantage of the self-aligned contact (hereinafter referred to as “SAC”) technique is that the misalignment margin of the photolithography process can be increased and the contact resistance can be reduced. For these reasons, emphasis has been placed upon the SAC technique.
FIG. 1
illustrates a cross-sectional view of a conventional semiconductor substrate having a plurality of gate electrodes and contact pads prepared in accordance with a conventional SAC technique. The configuration schematically shown in
FIG. 1
is formed by the following process steps. A device isolation region
3
is formed over a semiconductor substrate
1
to define active regions and inactive regions. The device isolation region
3
may be formed by any suitable method well-known in the art for example, shallow trench isolation and local oxidation of silicon. A gate oxide layer (not shown) is formed by a conventional method, e.g., a thermal oxidation method. A gate electrode conductive layer
4
a
and a gate capping insulating layer
4
b
are laminated over the gate oxide layer in this order. The gate capping layer
4
b
has an etch selectivity with respect to subsequently deposited interlayer insulating film
6
. Then, the well-known photolithography process is conducted to form gate pattern
4
.
Using the gate pattern
4
as a mask, low concentration impurity ions are implanted into the active region of the semiconductor substrate
1
. A gate spacer
5
is formed on sidewalls of the gate pattern
4
by the process of depositing a silicon nitride layer and etching back thereof. The gate spacer
5
also has an etch selectivity with respect to the subsequently deposited interlayer insulating film
6
. Thereafter, using the gate pattern
4
and spacer
5
, high concentration impurity ions are implanted into the active region of the semiconductor substrate
1
.
An interlayer insulating film
6
is deposited over the resulting semiconductor substrate
1
. A photoresist pattern (not shown) then is deposited over the interlayer insulating film
6
. Using the photoresist pattern, exposed interlayer insulating film
6
is etched to form a plurality of contact holes
7
a
and
7
b
. The photoresist pattern typically has openings of circular or elliptical configuration.
After removing the photoresist pattern, the contact holes
7
a
and
7
b
are filled with conductive material such as polysilicon. The polysilicon layer then is planarized by conventional methods such as chemical mechanical polish (CMP) or etch-back to thereby form a plurality of contact pads
8
a
and
8
b
, i.e., bit line contact pad
8
b
and storage node contact pads
8
a.
When the interlayer insulating layer for SAC formation is etched, it is possible that etch stop phenomenon (which denotes that etching by-products cannot easily diffuse out from the SAC opening, so that the rate of SAC etching can significantly slow down) can arise due to the high aspect ratio of the SAC opening. To solve the etch stop phenomenon, the etching must be performed under the condition to suppress the formation of the etching by-product (e.g., polymer) and to increase the etching time. However, if such etching conditions are carried out, the gate capping layer and gate spacer are etched during the etching step, thereby resulting in a short between the SAC pads and gate electrodes.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problems, and it is therefore a feature of the present invention to provide a method for forming a reliable SAC in a semiconductor device without attacking gate spacers and thereby preventing a bridge between gate electrodes and later-formed SAC pads.
In accordance with the present invention, there is provided a method of forming a SAC opening concurrently with the formation of gate spacers. More specifically, after forming the stacked gate pattern with gate electrodes and capping layers thereon, an insulating layer for the gate spacers is deposited thereon. An interlayer insulating layer then is deposited over the insulating layer. The interlayer insulating layer has an etch selectivity with respect to the capping layer and insulating layer. For example, the interlayer insulating layer preferably is made of an oxide layer and the capping layer and insulating layer preferably are made of a nitride layer. A mask pattern is then formed on the interlayer insulating layer, and the interlayer insulating layer and the insulating layer are etched down to the surface of the semiconductor substrate between the stacked gate patterns using the mask pattern, to form a plurality of contact holes while concurrently forming spacers on the sidewalls of the stacked gate patterns.


REFERENCES:
patent: 5484741 (1996-01-01), Bergemont
patent: 5817562 (1998-10-01), Chang et al.
patent: 6037223 (2000-03-01), Su et al.
patent: 6069077 (2000-05-01), Lee et al.
patent: 6074915 (2000-06-01), Chen et al.
patent: 2333179 (1999-07-01), None
Y. Kohyama, et al. A Fully Printable, Self-Aligned and Planarized Stacked Capacitor, etc. 1997 Symposium on VLSI Tech. Disgest of Technical Papers, pp. 17 and 18.

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