Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-08
2004-10-19
Chen, Jack (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S585000, C438S595000, C438S655000
Reexamination Certificate
active
06806154
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to the field of microelectronic fabrication. More particularly, the invention relates to a salicided metal oxide silicon field effect transistor (MOSFET) structure with a tunable oxynitride (SiN
x
O
y
) spacer.
2. Discussion of the Related Art
Prior art MOSFETs are known to those skilled in the art. In the case of deep sub ¼ micron salicided MOSFETs, oxynitride anti-reflective coatings have been used on top of the polycrystalline silicon layers for advanced lithography processes (e.g., such as deep ultra-violet, DUV). In more detail, a polycrystalline silicon layer that will be patterned to define the gates of the MOSFETs is covered with the oxynitride anti-reflective coating. The anti-reflective coating is then covered with a photoresist. The anti-reflective coating improves the resolution of the photo lithographic process. After the photoresist is developed, the exposed portions of the anti-reflective coating, and subsequently, the exposed portions of the polycrystalline silicon will be (plasma) dry-etched away. After the polycrystalline silicon layer is patterned to define the gates, N
−
/P
−
source and drain regions are formed in the exposed underlying silicon substrate. An oxide layer is then deposited and anisotropically etched to form spacers adjacent the patterned gates. This is followed by N
+
/P
+
source and drain region formation, and then HF cleaning. A metal layer is then deposited on polycrystalline (gate) and silicon (source/drain) areas and heated, thereby causing portions of the metal layer that are in contact with underlying silicon structures to react with the silicon in those structures to form salicide (self aligned silicide). Those portions of the metal layer that are in contact with the oxide spacers do not react to from a salicede. This is how the silicide is self aligned between the gate and the source/drain.
A problem with this technology has been that the oxide spacers are attacked by the HF cleaning before the metal layer can be deposited. The HF cleaning is a necessary step to remove native oxide. Native oxide will retard or even prohibit the metal/Si reaction and will result in both a high junction resistance and leakage. When the oxide spacers are attacked by the HF cleaning, the accuracy (resolution) of the photo lithographic process can suffer. In to more detail, prolonged HF cleaning can erode the oxide spacers, thereby exposing the lightly doped junction area underneath the original spacer area. The extent of the area of lightly doped junction that is exposed depends on the duration of the HF cleaning which determines how much of the spacer material is eroded from the exposed sides.
One unsatisfactory approach, in an attempt to solve the loss of accuracy problem involves forming the spacers from silicon nitride. Silicon nitride is resistant to HF. However, the dielectric constant of silicon nitride is high and this approach increases the fringing capacitance of the resulting MOSFET, which degrades the device dynamic (speed) performance. Therefore, what is required is an HF resistant spacer that does not degrade the device dynamic performance.
Another problem with both the silicon oxide spacer and silicon nitride spacer approaches is that the use of either of these materials creates a process incompatibility with regard to removal of the oxynitride anti-reflective coating. Either approach requires that a both a portion of the spacer layer and all of the anti-reflective coating be removed before the metal layer is deposited. However, the oxynitride anti-reflective coating is resistant to the etchants that are used to pattern the silicon oxide and silicon nitride spacers. This requires the spacer layer to be patterned during one etching step and the anti-reflective coating to be removed during another etching step. These two etching steps require two different etchants with different process conditions, and more than twice as much time. More importantly, the extra etching step will inevitably attack the exposed source/drain area since these area have been exposed during the first spacer etch process. This attack causes serious junction leakage, and serious junction recess (erosion). Therefore, what is also needed is a solution that reduces the number of etching steps, thereby enhancing production efficiency and minimizing Si (source/drain) area attack.
Heretofore, the requirements of HF resistance, high speed performance, production efficiency, and minimization of Si (source/drain) area attack have not been fully met. What is needed is a solution that simultaneously addresses all of these requirements.
SUMMARY OF THE INVENTION
Additional goals of the invention are: (1) to provide an HF resistant spacer; (2) to maintain the device's dynamic performance; (3) to improve production efficiency; and (4) to minimize the vulnerability of the source/drain junction to attack.
In accordance with these goals, there is a particular need for a self aligned silicide (salicide) MOSFET structure with tunable oxynitride spacers. The silicide is self aligned by the geometric extent of the oxynitride spacers. The spacers are made of the same material as the anti-reflective coating. Thus, it is rendered possible to simultaneously satisfy the above-discussed requirements of HF resistance, high speed performance, production efficiency, and minimizing Si (source/drain junction) area attack which, in the case of the prior art, are mutually contradicting and cannot be simultaneously satisfied.
A first aspect of the invention is implemented in an embodiment that is based on a salicided MOSFET structure, comprising: a source region; a first salicide portion adjacent said source region; a first oxynitride spacer connected to said first salicide portion; a polycrystalline silicon gate having a first side surface adjacent said first oxynitride spacer, a top surface, and a second side surface; a second salicide portion adjacent said top surface and connected to said first oxynitride spacer; a second oxynitride spacer adjacent said second to side surface and connected to said second salicide portion; a third salicide portion connected to said second oxynitride spacer; and a drain region adjacent said third salicide portion and connected to said second oxynitride spacer.
A second aspect of the invention is implemented in an embodiment that is based on a method of fabricating a salicided MOSFET structure, comprising: forming a coating on a gate layer, said coating including a first material; patterning said gate layer through said coating so as to define a gate, said coating remaining on a first portion of a surface of said gate; depositing a first layer on i) said coating, ii) a second portion of said surface of said gate, iii) a third portion of said surface of said gate, iv) a surface of a source region operably coupled to said gate, and v) a surface of a drain region operably coupled to said gate, said first layer including said first material; removing substantially all of said coating and a fraction of said first layer so as to expose said first portion of said surface of said gate, said surface of said source region, and said surface of said drain region, while forming a first spacer adjacent said second portion of said surface of said gate and a second spacer adjacent said third portion of said surface of said gate; cleaning said first portion of said surface of said gate, said surface of said source region, and said surface of said drain region; depositing a second layer on a) said first portion of said surface of said gate, b) said source region, and c) said drain region, said second layer including a salicide forming reactant; and converting a part of said second layer into a salicide by reacting said second layer with silicon in 1) said gate, 2) said source region, and 3) said drain region with said salicide forming reactant.
REFERENCES:
patent: 3558348 (1971-01-01), Rand
patent: 4702936 (1987-10-01), Maeda et al.
patent: 4837185 (1989-06-01), Y
Chen Jack
Integrated Device Technology Inc.
Okumoto, Esq. Victor H.
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