Method for forming a polysilicon spacer with a vertical profile

Details Method for forming a polysilicon spacer with a vertical profile Method for forming a polysilicon spacer with a vertical profile

2003-03-18

2004-07-13

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S706000

Reexamination Certificate

active

06762096

ABSTRACT:

BACKGROUND OF THE INVENTION
1 Field of the Invention
The invention relates to a method of forming a control gate of a flash memory, and more particularly to a method of forming a polysilicon spacer with a vertical profile.
2 Description of the Related Art
A flash memory cell comprises a floating gate for storing charges and a control gate for controlling the voltage of a world line, in which the voltages of the world line and source/drain electrodes are coordinated to control the charge-stored capacity of the floating gate and decide the on/off state of a transistor. Thus, the flash memory is also called an erasable programmable read only memory, or EPROM. For early flash memory devices, a gate structure is formed by stacking the control gate on the floating gate. As for the recent flash memory device, a gate structure is formed by laterally arranging the control gate and the floating gate, in which a polysilicon spacer is formed on the sidewall of the floating gate to serve as a control gate.
FIGS. 1A and 1B
are cross-sections showing a conventional method of forming a control gate. In
FIG. 1A
, a semiconductor silicon substrate
10
is provided with two floating gates
12
A and
12
B embedded in a insulating structure
14
, and a source polysilicon layer
16
formed in the insulating structure
14
between the two floating gates
12
A and
12
B. Then, a polysilicon layer
18
is deposited on the entire surface of the semiconductor silicon substrate
10
. Next, in
FIG. 1B
, using an etching back process, the polysilicon layer
18
is removed from the top of the insulating structure
14
and the source polysilicon layer
16
, and the polysilicon layer
18
left on the outer sidewalls of the floating gates
12
A and
12
B becomes two polysilicon spacers
19
, respectively. Therefore, each of the polysilicon spacers
19
serves as a control gate pattern.
Since the polysilicon layer
18
has a deposited surface with an undulating profile depending on the topography of the semiconductor silicon substrate
10
, this limitation causes the polysilicon spacer
19
to have an arc-shaped profile by the conventional etching back process. The polysilicon spacer
19
fails to form a control gate pattern with a vertical profile, and the arc-shaped profile can not conform to requests in sequential processes.
SUMMARY OF THE INVENTION
Accordingly, an object of the invention is to provide a method of forming a polysilicon spacer with a vertical profile to serve as a control gate of a flash memory.
To achieve these and other advantages, the invention provides a method of forming a polysilicon spacer with a vertical profile. A dielectric layer and a sacrificial layer are successively deposited to cover the entire surface of a polysilicon layer that covers an insulating structure. Then, CMP is used to remove parts of the sacrificial layer, the dielectric layer and the polysilicon layer to reach a planarized surface. Then, a part of the polysilicon layer outside the insulating structure is removed to make the insulating structures protrude from the top of the polysilicon layer. After removing the sacrificial layer, forming a second oxide layer on the exposed surface of the polysilicon layer and removing the dielectric layer, dry etching is used to remove the polysilicon layer that is not covered by the second oxide layer. The polysilicon layer left under the second oxide layer serves as a polysilicon spacer with a vertical profile.
Further scope of the applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.


REFERENCES:
patent: 5451543 (1995-09-01), Woo et al.
patent: 5756396 (1998-05-01), Lee et al.
patent: 6448649 (2002-09-01), Lee et al.

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