Method for forming a poly load resistor

Details Method for forming a poly load resistor Method for forming a poly load resistor

1996-08-26

1998-01-06

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438381, 438382, H01L 218244

Patent

active

057054363

ABSTRACT:
A physical implementation and method for achieving it are described for a load resistor and bus line subcircuit such as might be used in an SRAM cell. This was achieved by using two layers of polysilicon. The first polysilicon layer has low resistivity and serves to make effective contact to the drain regions of the FETs involved in the circuit. The second polysilicon layer has high resistivity and is used to form the load resistor as well as the collector bus line and resistor-drain connection. Formation of the latter two objects is achieved by providing a refractory metal underlay to the second polysilicon layer in the appropriate areas and then heating the structure so as to convert said refractory metal to its silicide. This process avoids the use of an ion implantation step during which some encroachment of the ions could occur, thereby retaining good control of the resistor dimensions.

REFERENCES:
patent: 5108945 (1992-04-01), Matthews
patent: 5164338 (1992-11-01), Graegor et al.
patent: 5381046 (1995-01-01), Cederbaum et al.
S. Wolf, "Silicon Processing For The VLSI Era-Volz", Lattice Press, Sunset Beach, CA, pp. 577, 578, 1990.

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