Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2002-08-14
2003-09-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S725000, C438S780000
Reexamination Certificate
active
06624055
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to the method for transferring patterns. Specifically, the invention is related to the method which effectively prevents the defects induced by damaged photoresist during the pattern transferring process.
2. Description of the Prior Art
In some semiconductor fabrications, N-type transistors and P-type transistors are formed with the following steps in sequence: forms a conductor layer on a substrate, doping numerous impurities into the conductor layer, and patterning the conductor layer. For example, after the conductor layer is formed, both the N-type transistor areas and the P-type transist are doped immediately. For example, after the conductor layer is formed, only the gate area of one type transistor is doped but the gate area of another type transistor is not doped, such that only some transistors have doped gate conductor layer but other transistors only have undoped gate conductor layer.
Such semiconductor fabrications usually are used to avoid the defects of the following processes, while the gates are formed by the pattern process before the doping process is performed. For example, because both the gates and the substrate are not covered after the pattern process and before the doping process, it is hard to precisely control the doping process to let only the gate conductor layer be doped but both the source and the drain be not doped, especially being hard to precisely control the doping process to let only partial gate conductor layer be doped.
However, such semiconductor fabrications also have the following defects:
Although the N-type transistors and the P-type transistors usually use same material to form their gate conductor layer, the doped density and the doped impurities often are different between them. Hence, because different doped materials usually have different etch details, such as etching rate and prefer etch recipe, even they are formed from the same undoped material, it is hard to precisely form P-type transistors and N-type transistors simultaneously if the doped details of P-type transistors are different than that of N-type transistors. For example, while the gate area of N-type transistors is doped but the gate area of the P-type transistors is not doped, each P-type gate usually is wider than each N-type gate even their patterns have same width in the corresponding photo-mask.
Because the substrate must be covered by an anti-reflection layer, such as a SiON layer, before the exposing process, it is desired to remove the anti-reflection layer after the etching process and then the damages of formed structures, such as formed gates, often are unavoidable. For example, while the phosphoric acid is used to remove the SiON layer, not only the gate conductor layers are etched by the phosphoric acid but also different gate conductor layers with different doped details have different etch damages.
It often is desired to perform a thermal treatment before the patterning process to re-distribute or diffuse the impurities doped into the conductor layer or the substrate through the conductor layer.
Clearly, both the fabrication steps and relative cost are increased.
Moreover, because the etch properties of different materials, such as doped polysilicon and undoped polysilicon, usually are different, an optimum etching recipe of one material usually is not effective for another material. Hence, while different parts of a substrate have different doped properties, it is hard to effectively etch the whole conductor layer on the whole substrate. Sometimes it is hard to etch different parts in a chamber simultaneously, sometimes it is impossible to etch different parts at the same time.
Besides, the conductor layer sometimes is not totally smooth, no matter is induced by the existent field oxide before the formation of the conductor layer or is induced by the unavoidable defect(s)of the fabrication of the conductor layer. Hence, the doping result sometimes is not uniform enough. For example, if the conductor layer is thinner on some parts of the substrate, the doping process for forming the doped gate conductor layer may also doping some impurities into these parts. Thus, for any transistor located in these parts, not only the gate conductor layer is doped but also both the source and the drain are doped, which is an unwanted defect.
SUMMARY OF THE INVENTION
One main object of this invention is to improve the conventional technology that patterns the gates before the impurities are doped, such that the previous defects induced by the conventional technology that dopes impurities before the gates be patterned.
Another main object of this invention is to provide a method for forming the plane structure, especially a forming plane structure method which could be used to archive the formed object.
One preferred embodiment of the invention is a semiconductor fabrication. Initially, provide a substrate and form both numerous first gates and numerous second gates on the substrate. Next, form a first cover layer to cover the substrate, the first gates and the second gates. Then, form a second cover layer to cover partial substrate, the second cover layer only covers the second gates but not covers any first gate. Sequentially, perform a doping process. Finally, remove both second cover layer and first cover layer.
Another preferred embodiment of the method is a method for forming a plane structure. First, provide a substrate. Then, form a liquid material on the substrate. Finally, remove partial liquid material by a spin-etch process to form a plane structure. Herein, the spin-etch process rotates both substrate and liquid material around an axis of substrate and applies a solvent on liquid material to remove partial liquid material simultaneously.
The other preferred embodiment of the invention is a method for forming a plane structure. First, provide a substrate. Next, form a photoresist layer on the substrate. Then, treat the photoresist layer by a part-expose process such that only the surface part of the photoresist layer is exposed. Finally, remove exposed part of the photoresist layer.
REFERENCES:
patent: 5244839 (1993-09-01), Baker et al.
patent: 5473187 (1995-12-01), Baker et al.
patent: 5569614 (1996-10-01), Kataoka et al.
patent: 5753940 (1998-05-01), Komoto
patent: 6020639 (2000-02-01), Ulrich et al.
patent: 6245640 (2001-06-01), Claussen et al.
patent: 6406994 (2002-06-01), Ang et al.
patent: 2001/0054735 (2001-12-01), Nagai
patent: 2002/0132393 (2002-09-01), Kraxenberger et al.
Huang Jui-Tsen
Hung Kuei-Chun
LandOfFree
Method for forming a plane structure does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a plane structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a plane structure will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3012094