Plastic and nonmetallic article shaping or treating: processes – Optical article shaping or treating – Utilizing plasma – electric – electromagnetic – particulate – or...
Reexamination Certificate
2000-05-09
2003-09-23
Vargot, Mathieu D. (Department: 1732)
Plastic and nonmetallic article shaping or treating: processes
Optical article shaping or treating
Utilizing plasma, electric, electromagnetic, particulate, or...
C264S001700
Reexamination Certificate
active
06623668
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a solid-state image pick-up device, and more particularly to a method of forming micro lenses of a solid-state image pick-up device.
A two-dimensional charge coupled device is one of the typical solid-state image pick-up devices. The two-dimensional charge coupled device has an image pick-up region on which a plurality of photodiodes are aligned in matrix, wherein each of the photodiodes converts an optical signal into an electrical signal. A micro lens is provided over each of the photodiodes to improve sensitivity of the photodiodes. The micro lens is hemispherical-shaped. A light or a photon is transmitted through the micro lens and injected into the photodiode, whereby the light is converted into a charge which corresponds to the amount of light or photon. The generated charge is then accumulated into the photodiode.
In Japanese patent publication No. 60-59752, there is disclosed a conventional method of forming micro lenses of a solid-state image pickup device.
FIGS. 1A through 1D
are fragmentary cross sectional elevation views illustrative of solid-state image pick-up devices involved in a conventional method of forming an alignment of micro lenses over photodiodes of the solid-state image pick-up device,
With reference to
FIGS. 1A and 1D
, a p-type well region
2
is formed over an n-type semiconductor substrate
1
. N-type photo receiving regions
3
are selectively formed in an upper region of the p-type well region
2
. N-type charge coupled device channel regions
4
are also selectively formed in the upper region of the p-type well region
2
, so that the n-type charge coupled device channel regions
4
are separated from the n-type photo receiving regions
3
. P+-type device isolation regions
5
are also selectively formed in the upper region of the p-type well region
2
, so that each of the p+-type device isolation regions
5
is positioned in contact with the n-type charge coupled device channel region
4
and the n-type photo receiving region
3
and also positioned between the n-type charge coupled device channel region
4
and the n-type photo receiving region
3
, whereby the n-type charge coupled device channel region
4
is isolated by the p+-type device isolation region
5
from the n-type photo receiving region
3
. A gate oxide film
6
is formed over the upper region of the p-type well region
2
, the n-type photo receiving regions
3
, the n-type charge coupled device channel regions
4
and the p+-type device isolation regions
5
. Polysilicon gate electrodes
7
are selectively formed on the gate oxide film
6
, wherein each of the polysilicon gate electrodes
7
extends to cover the n-type charge coupled device channel region
4
and a closer half region of the p+-type device isolation regions
5
to the n-type charge coupled device channel region
4
as well as cover the upper region of the p-type well region between the n-type photo receiving region
3
and the n-type charge coupled device channel region
4
. The polysilicon gate electrodes
7
do not extend to cover the n-type photo receiving region
3
and the closer half region of the p+-type device isolation region
5
to the n-type photo receiving region
3
. Shielding layers
8
are formed which cover the polysilicon gate electrodes
7
and the gate oxide film
6
around the polysilicon gate electrodes
7
except over center regions of the n-type photo receiving regions
3
, so as to allow lights to be injected or incident into the center regions of the n-type photo receiving regions
3
. The above structure from the substrate
1
to the shielding layers
8
will hereinafter be referred to as a base region
110
. A planarized insulation layer
111
is entirely formed over the base region
110
. The planarized insulation layer
111
comprises either a silicon oxide layer or a transparent resin layer. The planarized insulation layer
111
is transparent to the light. Each gap between adjacent two of the shielding layers
8
is filled with the planarized insulation layer
111
. A plurality of micro lenses
112
are formed on the planarized surface of the planarized insulation layer
111
, so that the micro lenses
112
are positioned over the n-type photo receiving regions
3
and also over the gaps between the shielding layers
8
. The light is transmitted through the micro lens
112
and the planarized insulation layer
111
in the gap between the shielding layers
8
and incident into the center region of the n-type photo receiving region
3
.
The above solid-state image pickup device with the micro lenses may be formed as follows.
With reference to
FIG. 1A
, a p-type well region
2
is formed over an n-type semiconductor substrate
1
. N-type photo receiving regions
3
are selectively formed in an upper region of the p-type well region
2
. N-type charge coupled device channel regions
4
are also selectively formed in the upper region of the p-type well region
2
, so that the n-type charge coupled device channel regions
4
are separated from the n-type photo receiving regions
3
. P+-type device isolation regions
5
are also selectively formed in the upper region of the p-type well region
2
, so that each of the p+-type device isolation regions
5
is positioned in contact with the n-type charge coupled device channel region
4
and the n-type photo receiving region
3
and also positioned between the n-type charge coupled device channel region
4
and the n-type photo receiving region
3
, whereby the n-type charge coupled device channel region
4
is isolated by the p+-type device isolation region
5
from the n-type photo receiving region
3
. A gate oxide film
6
is formed over the upper region of the p-type well region
2
, the n-type photo receiving regions
3
, the n-type charge coupled device channel regions
4
and the p+-type device isolation regions
5
. Polysilicon gate electrodes
7
are selectively formed on the gate oxide film
6
, wherein each of the polysilicon gate electrodes
7
extends to cover the n-type charge coupled device channel region
4
and a closer half region of the p+-type device isolation regions
5
to the n-type charge coupled device channel region
4
as well as cover the upper region of the p-type well region between the n-type photo receiving region
3
and the n-type charge coupled device channel region
4
. The polysilicon gate electrodes
7
do not extend to cover the n-type photo receiving region
3
and the closer half region of the p+-type device isolation region
5
to the n-type photo receiving region
3
. Shielding layers
8
are formed which cover the polysilicon gate electrodes
7
and the gate oxide film
6
around the polysilicon gate electrodes
7
except over center regions of the n-type photo receiving regions
3
, so as to allow lights to be injected or incident into the center regions of the n-type photo receiving regions
3
. The above structure from the substrate
1
to the shielding layers
8
will hereinafter be referred to as a base region
110
.
With reference to
FIG. 1B
, a planarized insulation layer
111
is entirely formed over the base region
110
. The planarized insulation layer
111
comprises either a silicon oxide layer or a transparent resin layer. The planarized insulation layer
111
is transparent to the light, Each gap between adjacent two of the shielding layers
8
is filled with the planarized insulation layer
111
.
With reference to
FIG. 1C
, a transparent thermo-setting resin material as a micro lens material is applied entirely on the planarized surface of the planarized insulation layer
111
. The transparent thermo-setting resin material is patterned by a photo-lithography technique to form micro lens patterns
112
a
which are positioned over the n-type photo receiving regions
3
and also over the gaps between the shielding layers
8
.
With reference to
FIG. 1D
, a heat treatment is carried out to cause thermal re-flow of the micro lens patterns
1
Murakami Ichiro
Nakashiba Yasutaka
Hayes & Soloway P.C.
NEC Electronics Corporation
Vargot Mathieu D.
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