Method for forming a planar and vertical semiconductor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C438S154000, C438S938000, C257S331000, C257S365000, C257S369000, C257S347000, C257S204000, C257S285000, C257S351000, C257S401000

Reexamination Certificate

active

07575975

ABSTRACT:
Forming a semiconductor structure includes providing a substrate having a strained semiconductor layer overlying an insulating layer, providing a first device region for forming a first plurality of devices having a first conductivity type, providing a second device region for forming a second plurality of devices having a second conductivity type, and thickening the strained semiconductor layer in the second device region so that the strained semiconductor layer in the second device region has less strain that the strained semiconductor layer in the first device region. Alternatively, forming a semiconductor structure includes providing a first region having a first conductivity type, forming an insulating layer overlying at least an active area of the first region, anisotropically etching the insulating layer, and after anisotropically etching the insulating layer, deposing a gate electrode material overlying at least a portion of the insulating layer.

REFERENCES:
patent: 6483171 (2002-11-01), Forbes et al.
patent: 6867433 (2005-03-01), Yeo et al.
patent: 6882025 (2005-04-01), Yeo et al.
patent: 7052964 (2006-05-01), Yeo et al.
patent: 7067370 (2006-06-01), Lee et al.
patent: 7101742 (2006-09-01), Ko et al.
patent: 7112495 (2006-09-01), Ko et al.
patent: 7180134 (2007-02-01), Yang et al.
patent: 2003/0040185 (2003-02-01), Jun
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0161886 (2004-08-01), Forbes et al.
patent: 2004/0256639 (2004-12-01), Ouyang et al.
patent: 2004/0259315 (2004-12-01), Sakaguchi et al.
patent: 2004/0266076 (2004-12-01), Doris et al.
patent: 2005/0017377 (2005-01-01), Joshi et al.
patent: 2005/0167652 (2005-08-01), Hoffmann et al.
patent: 2005/0167750 (2005-08-01), Yang et al.
patent: 2005/0218427 (2005-10-01), Joshi et al.
patent: 2005/0224897 (2005-10-01), Chen et al.
patent: 2005/0227498 (2005-10-01), Furukawa et al.
patent: 2005/0263831 (2005-12-01), Doris et al.
patent: 2005/0280121 (2005-12-01), Doris et al.
patent: 2006/0011984 (2006-01-01), Currie
patent: 2006/0014366 (2006-01-01), Currie
patent: 2006/0113603 (2006-06-01), Currie
patent: 2006/0113605 (2006-06-01), Currie
patent: 2006/0157687 (2006-07-01), Doyle et al.
patent: 2006/0180866 (2006-08-01), Zhu et al.
patent: 2006/0214226 (2006-09-01), Chen et al.
patent: 2007/0052041 (2007-03-01), Sorada et al.
International Search Report.
Monfray et al., “50nm-Gate All Around (GAA)—Silicon On Nothing (SON)—Devices: A Simple Way to Co-Integration of GAA Transistors Within Bulk MOSFET Process,” IEEE 2002 Symposium On VLSI Technology Digest Technical Papers, pp. 108-109.
Borland, “Novel Device Structures by Selective Epitaxial Growth (SEG),” IEEE, 4 pgs. (1987).
Terada et al, “A New Dram Cell with a Transistor on a Lateral Epitaxial Silicon Layer (TOLE Cell),” IEEE Transactions on Electron Devices, vol. 27, No. 9, Sep. 1990, pp. 2052-2057.
Terada et al., “A CMOS/Partial-SOI Structure for Future ULSIs,” IEEE SOS/SOT Technology Workshop, p. 37 (1988).
Monfray et al., “SON (Silicon-On-Nothing) P-MOSFETs With Totally Silicided (CoSi2) Polysilicon on 5nm-thick Si-films: The Simplest Way to Integration of Metal Gates on Thin FD Channels,” IEEE, p. 263-266 (2002).
Monfray et al., “Highly-performant 38nm SON (Silicon-On-Nothing) P-MOSFETS With 9nm-thick Channels,” 2002 IEEE International SOI Conference, pp. 20-22.
Monfray et al., “First 80nm SON (Silicon-On-Nothing MOSFETS With Perfect Morphology and High Electrical Performance,” IEEE, pp. 29.7.1-29.7.4 (2001).
Jurczak et al., “Silicon-on-Nothing (SON)—an Innovative Process for Advanced CMOS,” IEEE Transactions on Electron Devices, vol. 47, No. 11, Nov. 2000, pp. 2179-2187.
Burghartz et al., “Partial-SOI Isolation Structure for Reduced Bipolar Transistor Parasitics,” IEEE Electron Device Letters, vol. 13, No. 8, Aug. 1992, pp. 424-425.
Kubota et al., “A New Soft-Error Immune Dram Cell With A Transistor On A Lateral Epitaxial Silicon Layer (TOLE Cell),” IEEE, 4 pgs. (1987).
Ogura, “Partial SOI/SON Formation by He+ Implantation and Annealing,” 2002 IEEE International SOI Conference, pp. 185-186.

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