Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2005-01-04
2005-01-04
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
Reexamination Certificate
active
06838354
ABSTRACT:
Dummy features (64, 65, 48a,48b) are formed within an interlevel dielectric layer (36). Passivation layers (32and54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48band30) from being penetrated from the air gaps (74). In addition, the passivation layers (32and54) overhang the underlying conductive regions (44, 48a, 48band30), thereby defining dummy features (65a, 65band67) adjacent the conductive regions (48a, 44and48b). The passivation layers (32and54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
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PCT/US03/30590 Invitation to Pay Additional Fees—Results of Partial International Search.
Filipiak Stanley Michael
Flake John C.
Goldberg Cindy K.
Lii Yeong-Jyh T.
Smith Bradley P.
Coleman W. David
Freescale Semiconductor Inc.
Vo Kim-Marie
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