Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-06-27
2000-08-29
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438981, H01L 21336
Patent
active
061107832
ABSTRACT:
A method for making an asymmetric MOS device having a notched gate oxide wherein a region of the gate oxide adjacent to either the source or drain is thinner than the remainder of the gate oxide. The resulting MOS device includes a channel under the notched region of the gate oxide with a relatively high concentration of mobile charge carriers.
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On Feb. 25, 1994, one of the inventors, Dr. James B. Burr, had dinnerwith M. Nagata, K, Sasaki, H. Hiraki, and O. Nishii of Hitachi Corporation and one of them discussed (with Dr. Burr) Dr. Burr's work on low threshold voltage CMOS devices. This meeting was conducted after Dr. Burr had given a talk at the annual Hitachi seminar held in Stanford, CA. During their dinner meeting, Dr. Burr and one of the gentlemen from Hitachi sketched some notes and figures showing possible MOS device structures. A copy of their notes and figures is provided in the attached Exhibit A. As can be seen, one sketch shown in Exhibit A shows what appears to be an NMOS device having "p++" regions under both the source drain.
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Murphy John
Niebling John F.
Sun Microsystems Inc.
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