Method for forming a multi-layer shallow trench isolation...

Details Method for forming a multi-layer shallow trench isolation... Method for forming a multi-layer shallow trench isolation...

2008-04-29

2009-11-03

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S428000, C438S427000, C438S424000, C438S508000

Reexamination Certificate

active

07611963

ABSTRACT:
A method for forming a multi-layer shallow trench isolation structure in a semiconductor device is described. In one embodiment, the method includes etching a shallow trench in a silicon substrate of a semiconductor device and forming a dielectric liner layer on a floor and walls of the shallow trench. The method further includes forming a first doped oxide layer in the shallow trench, the first layer formed by vapor deposition of precursors including a source of silicon, a source of oxygen, and sources of doping materials at a first processing condition and forming a second doped oxide layer above the first doped oxide layer by vapor deposition using precursors of silicon and doping materials, at a second processing condition, different from the first processing condition.

REFERENCES:
patent: 6465325 (2002-10-01), Ridley et al.
patent: 7160787 (2007-01-01), Heo et al.
patent: 7482246 (2009-01-01), Eun
patent: 2004/0192009 (2004-09-01), Belyansky et al.
patent: 2004/0198019 (2004-10-01), Yasui et al.
patent: 2009/0020845 (2009-01-01), Shin et al.

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