Method for forming a multi-layer low-K dual damascene

Details Method for forming a multi-layer low-K dual damascene Method for forming a multi-layer low-K dual damascene

2006-10-31

2006-10-31

Le, Thao P. (Department: 2818)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S778000, C438S641000, C257SE21579

Reexamination Certificate

active

07129164

ABSTRACT:
A damascene structure and method for forming the same in a multi-density dielectric insulating layer the method including providing a substrate; forming at least a first layer comprising silicon oxide according to a first process having a first density; forming at least a second layer comprising silicon oxide according to a second process over the first layer having a second density less than the first density; etching a damascene opening through a thickness portion of the at least a first and the at least a second layer; and, filling the damascene opening to form a metal filled damascene.

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patent: 6893956 (2005-05-01), Ruelke et al.
patent: 2005/0070128 (2005-03-01), Xia et al.

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