Method for forming a MOS structure having sidewall source/drain

Details Method for forming a MOS structure having sidewall source/drain Method for forming a MOS structure having sidewall source/drain

1997-11-21

2000-03-14

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438302, 438525, H01L 21336

Patent

active

060372311

ABSTRACT:
A MOS device is provided with a reduced source and drain area. This is accomplished by first providing a MOS device with a buried gate region. The buried gate region is located on top of a channel region, which runs horizontally along the bottom of the gate trench. The source and drain regions are aligned vertically an parallel to the outside sidewalls of the buried gate region. Sidewall protectors are provided between the gate and lateral source and drain regions on the inside sidewalls of the gate trench. Additionally, a process for manufacturing the above described device is also disclosed.

REFERENCES:
patent: 5498564 (1996-03-01), Geissler et al.
patent: 5578508 (1996-11-01), Baba et al.

Affiliated with

Also associated with

Rating

Method for forming a MOS structure having sidewall source/drain does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a MOS structure having sidewall source/drain , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a MOS structure having sidewall source/drain will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-168805