Method for forming a MOS device with self-compensating V.sub.T -

Details Method for forming a MOS device with self-compensating V.sub.T - Method for forming a MOS device with self-compensating V.sub.T -

1999-02-03

2000-06-27

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438303, H01L 21336

Patent

active

060806303

ABSTRACT:
The present invention provides a method for forming a MOS device having self-compensating threshold adjust implants and reduced junction capacitance. A semiconductor substrate of a first conductivity type is provided. A gate oxide is formed on the surface of the semiconductor substrate, and a polysilicon gate is formed on the surface of the gate oxide. A first implant of a dopant of the first conductivity type is performed so as to form self-compensating implant regions in the semiconductor substrate on opposite sides of the gate. Disposable sidewall spacers are then formed around the polysilicon gate. A second implant of a dopant of a second conductivity type is performed so as to create highly-doped source/drain regions which are self-aligned to the sidewall spacers. The substrate with self-compensating implant regions and the highly-doped source/drain regions is then subject to a rapid thermal anneal (RTA) process so as to activate the dopant in the self-compensating implant regions and the highly-doped source/drain regions. The dopant within the self-compensating regions diffuses laterally under the polysilicon gate to define pockets. Thereafter, the disposable sidewall spacers are removed. Finally, a third implant of a dopant of the second conductivity type is performed so as to create lightly-doped source/drain regions in the self-compensating implant regions on opposite sides of the gate.

REFERENCES:
patent: 5466957 (1995-11-01), Yuki et al.
Okamura, K., Shirahata, M., Okudaira, T., Hachisuka, A., Arima, H., Matsukawa, T., and Tsubouchi, N., "A Novel Source-to-Drain Nonuniformly Doped Channel (NUDC) MOSFET for High Current Drivability and Threshold Voltage Controllability", IEDM 90, pp. 391-394.

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