Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Utility Patent
1999-08-16
2001-01-02
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S300000, C438S301000, C438S302000, C438S303000, C438S306000, C438S197000, C438S221000, C438S230000, C438S585000, C438S589000
Utility Patent
active
06169003
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to methods of forming metal oxide semiconductor field effect transistors (MOSFET) devices and specifically to those having an elevated source and drain, and more pointedly to those having a self-aligned channel implant.
BACKGROUND OF THE INVENTION
As integrated circuits (IC) become smaller and smaller through miniaturization, their decreased dimensions have presented additional problems and difficulties. For example, as their horizontal dimensions shrink to fit more and more field effect transistors (FET), for example, onto a single IC chip, the concomitant FET vertical dimensions also shrink channel lengths under the gate electrode which creates so-called short channel effects. Examples of short channel effects are: channel-length modulation, velocity saturation, mobility degradation, source/drain resistance, punchthrough, drain induced barrier lowering, and dependence of threshold voltage (V
t
) on device geometry. Techniques have been developed to counter these short channel effects. For example anti-punchthrough buried channel implants are placed in the substrate to counteract punchthrough effects.
For example, U.S. Pat. No. 5,773,348 to Wu describes a method of fabricating a short-channel MOS device that may include an anti-punchthrough stopping implantation to prevent punchthrough between the source and drain.
U.S. Pat. No. 5,538,913 to Hong describes a process for fabricating a MOS transistor having a full-overlap LDD structure that is suitable for semiconductor circuit integration and provides improved operational characteristics.
U.S. Pat. No. 5,434,093 to Chau et al. describes a method for forming narrow length transistors by the use of spacers within a trench formed in a first layer over a semiconductor substrate. A self-aligned punchthrough stopper may be implanted beneath the channel in the semiconductor substrate to raise the source/drain punchthrough voltage of the transistor and to reduce the capacitance between the source and the drain.
U.S. Pat. No. 5,489,543 to Hong describes a method employing self-alignment to form a metal oxide semiconductor (MOS) structure having a localized anti-punchthrough region which decreases the junction capacitance of source/drain regions, thereby helping to increase the operational speed of the resulting MOS transistors.
U.S. Pat. No. 5,429,956 to Shell et al. describes a structure and method for fabricating a FET having an improved drain to source punchthrough properties by the use of a self-aligned anti-punchthrough implant channel under and aligned to the FET's gate electrode.
U.S. Pat. No. 5,817,558 to Wu describes a semiconductor processing method for forming self-aligned T-gate LDD device having an ultra-short recessed gate and an anti-punchthrough layer.
U.S. Pat. No. 5,677,218 to Tseng describes a method of forming a local threshold voltage ion implantation to reduce the junction capacitance in a semiconductor device.
U.S. Pat. No. 5,599,728 to Hu et al. describes a method of making a self-aligned high speed MOSFET device having a punchthrough stopper region.
U.S. Pat. No. 5,670,401 to Tseng describes a process for fabricating a deep submicron MOSFET featuring a self-aligned local threshold voltage adjust region in a semiconductor substrate with the threshold voltage
U.S. Pat. No. 5,801,075 to Gardner et al. describes a method of forming an insulated gate FET using metal spacers to form a channel length significantly smaller than the trench length.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming a FET with a self-aligned channel implant.
Another object of the present invention is to provide a method of forming a FET having an elevated source and drain, and having a self-aligned channel implant.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a method of forming a FET with an having a self-aligned pocket implant, comprising the following steps. A substrate is formed having a substrate dielectric layer thereon and a first oxide layer over the substrate dielectric layer. The first oxide layer having an upper surface. A trench is formed through the oxide layer, the substrate dielectric layer, and partially through the substrate. The trench having a bottom and side walls. A second oxide layer is formed along the bottom and said side walls of said trench within the substrate. A dopant is selectively ion implanted into the substrate is achieved to form lightly doped layers adjacent the side walls of the trench within the substrate. A self-aligned channel implant and a pocket implant are ion implanted at predetermined respective depths in the substrate below the trench bottom is achieved. Side-wall spacers on the side walls of the trench are then formed with the side-wall spacers each having a top surface below the upper surface of the first oxide layer. A gate dielectric layer is formed on the bottom of the trench between the side-wall spacers. A planarized gate electrode is formed that has an upper surface substantially coextensive with the upper surface of the first oxide layer. The first oxide layer and the substrate dielectric layer are removed. A dopant is ion implanted into the substrate to form heavily doped layers adjacent the side wall spacers. In an alternate embodiment, inter alia, the LDD source and drain portions are formed after HDD source and drain portions formation and after the side-wall spacers are removed.
REFERENCES:
patent: 5429956 (1995-07-01), Shell et al.
patent: 5434093 (1995-07-01), Chau et al.
patent: 5489543 (1996-02-01), Hong
patent: 5538913 (1996-07-01), Hong
patent: 5599728 (1997-02-01), Hu et al.
patent: 5670401 (1997-09-01), Tseng
patent: 5677218 (1997-10-01), Tseng
patent: 5773348 (1998-06-01), Wu
patent: 5801075 (1998-09-01), Gardner et al.
patent: 5817558 (1998-10-01), Wu
Hu Chu-Wei
Weng Jine-Wen
Ackerman Stephen B.
Hack Jonathan
Niebling John F.
Saile George O.
Stoffel William J.
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