Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-30
2003-06-24
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S275000, C438S283000
Reexamination Certificate
active
06583013
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of integrated circuits, and more particularly to an improved method for forming a mixed voltage circuit having complementary devices.
BACKGROUND OF THE INVENTION
Modern electronic equipment such as televisions, telephones, radios and computers are generally constructed of solid state devices. Solid state devices are preferred in electronic equipment because they are extremely small and relatively inexpensive. Additionally, solid state devices are very reliable because they have no moving parts, but are based on the movement of charge carriers.
Solid state devices may be transistors, capacitors, resistors, and other semiconductor devices. Typically, such devices are formed in and on a substrate and are interconnected to form an integrated circuit. The integrated circuit may be a mixed voltage circuit that has core devices which operate at low voltage to accommodate small device size and to minimize power consumption and heat generation, and input/output (I/O) devices which operate at a higher voltage to interface with other higher voltage devices.
For a complementary metal oxide semiconductor (CMOS) mixed voltage circuit, the core devices are typically field effect transistors with a thin gate dielectric and a low threshold voltage while the I/O devices are typically field effect transistors with a thick dielectric and a high threshold voltage. To optimize performance of both core and I/O devices, masking processes in addition to roadmap CMOS design have been used to provide the dual gate dielectric thickness and to separately form source and drain extensions and pockets for the core and I/O devices. Such additional masking processes are expensive and greatly increase the cost of CMOS mixed voltage circuits.
Efforts to reduce the cost of CMOS mixed voltage circuits have concentrated on minimizing masking processes by co-optimizing the formation of source and drain extensions and pockets for the core and I/O devices using a single masking process. Co-optimization approaches, however, typically fail to achieve high performance core devices because the graded or deeper junctions required for I/O device reliability severely degrades the drive current performance of the core devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for forming a mixed voltage circuit having complementary devices is provided that substantially eliminates or reduces disadvantages or problems associated with previously developed systems and methods. In particular, the present invention provides a low cost mixed voltage circuit with improved device performance.
In one embodiment of the present invention, a mixed voltage circuit is formed by providing a substrate having a first region for forming a first device, a second region for forming a second device complementary to the first device, and a third region for forming a third device that operates at a different voltage than the first device. A gate layer is formed outwardly of the first, second, and third regions. While maintaining a substantially uniform concentration of a dopant type in the gate layer, a first gate electrode is formed in the first region, a second gate electrode is formed in the second region, and a third gate electrode is formed in the third region. The third region is protected while implanting dopants into the first region to form source and drain features for the first device. The first region is protected while implanting dopants into the third region to form disparate source and drain features for the third device.
Technical advantages of the present invention include providing an improved method for forming a mixed voltage circuit. In particular, performance of the mixed voltage devices in the circuit is improved without increasing fabrication costs. This is accomplished by omitting a gate implant mask from the fabrication process and instead using separate masks to optimize source and drain features for the low voltage core devices and higher voltage input/output (I/O) devices. The resulting mixed voltage circuit has high I/O device reliability and low core device resistance.
Other technical advantages will be readily apparent to one skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 6020227 (2000-02-01), Bulucea
patent: 6143594 (2000-11-01), Tsao et al.
patent: 6380016 (2002-04-01), Kohler
Jacobs Jarvis B.
Rodder Mark S.
Hoel Carlton H.
Perkins Pamela E
Zarabian Amir
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