Method for forming a mixed-signal CMOS circuit that includes non

Details Method for forming a mixed-signal CMOS circuit that includes non Method for forming a mixed-signal CMOS circuit that includes non

1996-07-25

1999-06-01

Booth, Richard A.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438585, H01L 218247

Patent

active

059083115

ABSTRACT:
A CMOS device that includes three-volt MOS transistor, five-volt MOS transistors, FLASH EPROM cells, poly resistors, and double-poly capacitors is formed in a single integrated CMOS process flow. The FLASH EPROM cells are formed as single-transistor memory cells that operate on low to very-low voltages.

REFERENCES:
patent: 5188976 (1993-02-01), Kume et al.
patent: 5477485 (1995-12-01), Bergemont et al.
patent: 5500387 (1996-03-01), Tung et al.
patent: 5511021 (1996-04-01), Bergemont et al.
patent: 5557567 (1996-09-01), Bergemont et al.
patent: 5587332 (1996-12-01), Chang et al.
patent: 5587949 (1996-12-01), Bergemont et al.
patent: 5594685 (1997-01-01), Bergemont et al.
patent: 5658812 (1997-08-01), Araki
patent: 5674762 (1997-10-01), See et al.
patent: 5702988 (1997-12-01), Liang
patent: 5712178 (1998-01-01), Cho et al.
Chi, M. et al., "Multi-level Flash/EPROM Memories: New Self-convergent Programming Methods for Low-voltage Applications," Tech. Digest of IEDM, pp. 271-274 (1995).
Paterson, J., "Adding Analog, EPROM and EEPROM modules to CMOS Logic Technology: How modular?" Tech. Digest of IEDM, pp. 413-416 (1989).
Lai, S.K et al., "Comparison and Trends in Today's Dominant E.sup.2 Technologies," Tech. Digest of IEDM, pp. 580-583 (1986).
Aritome, S. et al., "Reliability Issues of Flash Memory Cells," invited paper, proceedings of the IEEE, vol. 81, No. 5, pp. 776-787 (May, 1993).
Codella, C.F. et al., "Halo Doping Effects in Submicron DI-LDD Device Design," Tech. Digest of IEDM, pp. 230-233 (1985).
Hori, A. et al., "A Self-Aligned Pocket Implantation (SPI) Technology for 0.2 .mu.m-Dual Gate CMOS," Tech. Digest of IEDM, pp. 641-644 (1991).
Cheng, H. et al., "Superior Low-Pressure-Oxidized Si.sub.3 N.sub.4 Films on Rapid-Thermal-Nitrided Poly-Si for High-Density DRAM's," IEEE Electron Device Letters, vol. 16, No. 11, pp. 509-511 (1995).
Wann, H. et al., "Suppressing Flash EEPROM Erase Leakage with Negative Gate Bias and LDD Erase Junction," Dept. of Elect. Engineering & Comp. Sci., Berkeley, CA, pp. 81-82 (1993).
Manos, Pete et al., "A Self-Aligned EPROM Structure with Superior Data Retention," IEEE Electron Device Letters, vol. 11, No. 7, pp. 309-311, Jul. 1990.
U.S. Application 08/654,103, filed May 28, 1996, Chi et al.

Affiliated with

Also associated with

Rating

Method for forming a mixed-signal CMOS circuit that includes non does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a mixed-signal CMOS circuit that includes non, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a mixed-signal CMOS circuit that includes non will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-951296