Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-07-20
2001-10-09
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S637000
Reexamination Certificate
active
06300189
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for forming a metal capacitor on a semiconductor wafer, and more particularly, to a method for forming a metal capacitor that is formed of metal-insulator-metal (MIM).
2. Description of the Prior Art
In semiconductor manufacturing processes, metal capacitors formed of metal-insulator-metal (MIM) are widely used in the design of the semiconductor devices. Because a MIM capacitor has low resistance and low parasitic capacitance, and has no problems in shifts of depletion induced voltage, MIM capacitors have become the main structure used for metal capacitors.
Please refer to FIG.
1
and FIG.
2
. FIG.
1
and
FIG. 2
are schematic diagrams of a method for forming a metal capacitor
26
on a semiconductor wafer
10
according to the prior art. As shown in
FIG. 1
, the semiconductor wafer
10
includes a substrate (not shown), and a dielectric layer
12
positioned on the substrate. In the prior art method, a chemical vapor deposition (CVD) process is performed to evenly deposit a metal layer on the surface of the dielectric layer
12
. After defining the patterns of the metal bottom plate
14
, an etching process is performed to remove excess portions of the metal layer so as to form the metal bottom plate
14
. An insulation layer and another metal layer are then deposited, in order, on the surface of the metal bottom plate
14
. A lithographic process is performed to define the patterns of a metal upper plate
18
, and the excess portions of metal layer and insulation layer are removed to form the inter-metal insulator (IMI)
16
and the metal upper plate
18
so as to finish the formation of the metal capacitor
26
.
As shown in
FIG. 2
, an inter-metal dielectric (IMD) layer
20
covers the metal capacitor
26
, and a chemical mechanical polishing (CMP) process is used to planarize the surface of the inter-metal dielectric layer
20
. A photoresist layer (not shown) is coated on the surface of the inter-metal dielectric layer
20
, and a lithographic process is performed to define the position of via holes
28
. The excess portions of the photoresist layer are then removed, and a dry etching process is performed, using the residual photoresist layer as a mask. The inter-metal dielectric layer
20
that is not covered by the mask is removed so as to form the via holes
28
. The residual photoresist layer is then stripped.
A sputtering process is performed to form a metal layer (not shown) that fills the via holes
28
. An etching back process is then performed to remove portions of the metal layer till the surface of the metal layer in the via holes
28
are aligned with the surface of the inter-metal dielectric layer
20
so as to form the via plugs
22
. A metal layer (not shown) is then evenly deposited on the surface of the inter-metal dielectric layer
20
, and an etching process is performed to form a metal wire
24
on top of the via plugs
22
. The via plugs
22
are used to electrically connect the metal wire
24
and the metal capacitor
26
.
In the prior art method, the metal capacitor
26
is formed on the semiconductor wafer
10
first, and several via plugs
22
are formed in the inter-metal dielectric layer
20
to electrically connect to the metal wire
24
. This method makes good use of the low resistance and low parasitic capacitance of the metal capacitor
26
. However, in order to reduce the resistance between the metal wire
24
and the metal capacitor
26
, and to increase the current transmission speed, a great deal of area and space on the semiconductor wafer
10
must be used to form several via plugs
22
. As shown in
FIG. 2
, in order to reduce the resistance between the metal capacitor
26
and the metal wire
24
, the prior art method needs most of the space of the inter-metal dielectric layer
20
to form the via plugs
22
. Waste of the area of wafer
10
may thus result. Furthermore, the prior art method needs additional regions on the wafer
10
to form the locally connected metal layer.
As the line width of semiconductor devices shrinks, how to increase the integration density of the devices on the semiconductor wafer
10
, and how to reduce the area used on the wafer
10
so as to promote throughout, has become an important issue in the field of semiconductor manufacturing.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method form forming a metal capacitor on a semiconductor wafer to increase the integration of semiconductor devices.
In a preferred embodiment, the semiconductor wafer includes a dielectric layer. A bottom plate recess is formed in the dielectric layer first, and a metal bottom plate is formed in the bottom plate recess. An insulation layer is formed on the metal bottom plate, and a via hole is formed in the insulation layer. A first metal layer is then formed on the insulation layer that fills the via hole so as to form a via plug. Finally, a metal upper plate is formed on the insulation layer, and a metal wire is formed on top of the via plug.
It is an advantage of the present invention that the metal bottom plate of the metal capacitor is embedded into the inter-metal dielectric layer, and further forms the metal wire and the metal upper plate simultaneously, so that the present invention reduces the space required for forming the metal capacitor to increase the integration density of devices on the semiconductor wafer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the various figures and drawings.
REFERENCES:
patent: 5926359 (1999-07-01), Greco et al.
patent: 6025226 (2000-02-01), Gambino et al.
patent: 6144051 (2000-11-01), Nishimura et al.
patent: 6166423 (2000-12-01), Gambino et al.
Hsu Winston
Nelms David
Nhu David
United Microelectronics Corp.
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