Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-21
2002-05-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S254000, C438S396000, C438S240000
Reexamination Certificate
active
06395601
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device; and, more particularly, to a method for forming a lower electrode for use in a semiconductor device by using an electroplating method.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) with at least one memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.
To meet the demand, there have been proposed several structures for the capacitor, such as a trench type or a stack type capacitor, which are arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing three-dimensionally arranged capacitor is a long and tedious one and consequently involves high manufacturing cost. Therefore, there is a strong demand for a new memory device that can reduce the cell area with securing a requisite volume of information without requiring complex manufacturing steps.
Since capacitance is a function of dielectric area and the dielectric constant of the dielectric material, there have been introduced a high K dielectric, e.g., barium strontium titanate (BST) or the like, as a capacitor thin film in place of conventional silicon oxide film or silicon nitride film to increase capacitance in a given area. However, the use of high dielectric constant materials presents a problem when using a conventional material like ruthenium (Ru) as an electrode. The Ru electrode creates leakage current in the capacitance device.
Therefore, platinum (Pt) is suitable for use as electrodes in this situation. However, if a novel metal such as Pt is applied to a capacitor as a lower electrode, there easily occurs a misalign problem between a contact plug and a storage node. On the other hand, if a barrier layer is adopted to prevent this problem, it is directly in contact with a high K capacitor dielectric, which will, in turn, serves as a source of a leakage current.
Thus, there remains a need for a method of forming an electrode compatible with a high K capacitor dielectric without representing the above-described problems.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein lower electrodes which are formed by using an electroplating method.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a semiconductor device for use in a memory cell, the method comprising the steps of: a) preparing an active matrix provided with at least one diffusion region and an insulating layer formed thereon; b) patterning the insulating layer into a predetermined configuration, thereby exposing the diffusion region; c) forming a metal silicide film on the exposed diffusion region; d) forming a barrier metal on the metal silicide film; e) forming a seed layer on the active matrix including the barrier metal; f) forming a dummy oxide layer on the seed layer; g) patterning a dummy oxide layer into a preset configuration, thereby exposing portions of the seed layer which are located above the barrier metal; h) filling the exposed portions of the seed layer with a conductive material to a predetermined thickness; and i) removing the dummy oxide layer and the seed layer which are not covered with the conductive material.
REFERENCES:
patent: 5566045 (1996-10-01), Summerfelt et al.
patent: 5585300 (1996-12-01), Summerfelt
patent: 6171899 (2001-01-01), Liou et al.
patent: 6211035 (2001-04-01), Moise et al.
patent: 6255187 (2001-07-01), Horii
patent: 6281142 (2001-08-01), Basceri et al.
patent: 6294425 (2001-09-01), Hideki
Hong Kwon
Yu Yong-Sik
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kennedy Jennifer M.
Niebling John F.
LandOfFree
Method for forming a lower electrode for use in a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for forming a lower electrode for use in a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a lower electrode for use in a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2820248