Method for forming a layer of metal silicide over the gates of a

Details Method for forming a layer of metal silicide over the gates of a Method for forming a layer of metal silicide over the gates of a

1996-05-16

1998-06-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438655, H01L 218238

Patent

active

057598860

ABSTRACT:
Surface-channel NMOS and PMOS transistors are formed in a CMOS compatible process by implanting the substrate to form source and drain regions at the same time that the gate is implanted to set the conductivity of the gate. Following this, a layer of dielectric is deposited and baked to densify and reflow the dielectric. The baked dielectric is then etched to expose the top surface of the gates. Next, a metallic layer is formed over the top surface of the gates. In accordance with the present invention, by forming the metallic layer after the dielectric layer has been baked, the degradation of the metallic layer that results from the baking is eliminated.

REFERENCES:
patent: 5010032 (1991-04-01), Tang et al.
patent: 5190888 (1993-03-01), Schwalke et al.
patent: 5212542 (1993-05-01), Okumura
patent: 5468669 (1995-11-01), Lee et al.

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