Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-11-20
2001-10-09
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S307000, C257S308000, C438S250000
Reexamination Certificate
active
06300653
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to planar capacitors within integrated circuits. More particularly, the present invention relates to high areal capacitance planar capacitors within integrated circuits.
2. Description of the Related Art
In addition to resistors, transistors and diodes, integrated circuits also often have formed within their fabrications capacitors. When formed within analog integrated circuits, capacitors typically provide for proper operation of those analog integrated circuits. When formed within digital integrated circuits, capacitors typically provide charge storage locations for individual bits of digital data.
Capacitors of varying dimensions and shapes may be formed within several locations within analog or digital integrated circuits. A particularly common type of capacitor formed typically, although not exclusively, within analog integrated circuits is a planar capacitor. A schematic cross-sectional diagram illustrating an integrated circuit having a planar capacitor formed therein is shown in FIG.
1
.
Shown in
FIG. 1
is a semiconductor substrate
10
upon and within whose surface is formed isolation regions
12
a
and
12
b
which define the active region of the semiconductor substrate
10
. Within the active region of the semiconductor substrate
10
is formed a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) comprising a gate electrode
16
aligned upon a gate oxide layer
14
, and a pair of source/drain electrodes
18
a
and
18
b
formed within the exposed portion of the active region of the semiconductor substrate
10
not occupied by the gate oxide layer
14
and the gate electrode
16
.
As also shown in
FIG. 1
, the planar capacitor within the integrated circuit comprises a first planar capacitor electrode
20
separated from a second planar capacitor electrode
24
by a planar capacitor dielectric layer
22
. As illustrated by
FIG. 1
, the planar capacitor is formed upon the surface of an isolation region of the semiconductor substrate
10
, as is typical in the art. The isolation region upon which is formed the planar capacitor is the isolation region
12
b.
Although the planar capacitor as illustrated in
FIG. 1
is a common and accepted fabrication of a planar capacitor within an integrated circuit, the planar capacitor as illustrated in
FIG. 1
is not without problems. In particular, as integrated circuit device dimensions have continued to decrease, it has become increasingly difficult to fabricate planar capacitors, such as the planar capacitor within the integrated circuit illustrated by
FIG. 1
, with adequate levels of capacitance within the decreasing levels of surface area afforded to those planar capacitors within advanced integrated circuits. Planar capacitors with increasing levels of areal capacitance are thus typically needed to yield planar capacitors of adequate capacitance for proper operation of advanced integrated circuits.
It is thus towards the goal of forming high areal capacitance planar capacitors within integrated circuits having limited surface area available for those planar capacitors, that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a method for forming within an integrated circuit a high areal capacitance planar capacitor.
A second object of the present invention is to provide a method in accord with the first object of the present invention, which method is also manufacturable.
In accord with the objects of the present invention there is provided a method for forming a high areal capacitance planar capacitor within an integrated circuit, as well as the high areal capacitance planar capacitor which results from the method. To form the high areal capacitance planar capacitor of the present invention, there is first provided a semiconductor substrate. Formed upon the semiconductor substrate is a first planar capacitor electrode, and formed upon the first planar capacitor electrode is a first planar capacitor dielectric layer. Formed then upon the first planar capacitor dielectric layer is a second planar capacitor electrode, and formed upon the second planar capacitor electrode is a second planar capacitor dielectric layer. Finally, there is formed upon the second planar capacitor dielectric layer a third planar capacitor electrode.
The present invention provides a method for forming within an integrated circuit a high areal capacitance planar capacitor. Through the method of the present invention there is provided a planar capacitor which has a second planar capacitor electrode which is: (1) separated from a first planar capacitor electrode by a first planar capacitor dielectric layer, and (2) separated from a third planar capacitor electrode by a second planar capacitor dielectric layer. The planar capacitor formed through the method of the present invention thus has approximately twice the capacitance of a conventional planar capacitor of equivalent areal dimension, since the planar capacitor of the present invention has a second planar capacitor electrode which serves as a common electrode within two adjoining planar capacitors occupying a surface area equivalent to the surface area occupied by a conventional planar capacitor.
The high areal capacitance planar capacitor of the present invention is readily manufacturable. The high areal capacitance planar capacitor of the present invention comprises a novel five layer capacitor structure which is formed through methods and materials which are otherwise conventional in the art of integrated circuit fabrication. To the extent that no new methods and materials are needed to form the high areal capacitance planar capacitor of the present invention, the high areal capacitance planar capacitor of the present invention is readily manufacturable.
In addition, if the five layers within the five layer capacitor structure of the high areal capacitance planar capacitor of the present invention are formed simultaneously with other patterned layers which would otherwise be formed within the integrated circuit within which is formed the high areal capacitance planar capacitor of the present invention, then significant manufacturing economy and efficiency is realized in forming the high areal capacitance planar capacitor of the present invention within the integrated circuit.
REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 5006481 (1991-04-01), Chan et al.
patent: 5201991 (1993-04-01), Lee
patent: 5262354 (1993-11-01), Cote et al.
patent: 5285092 (1994-02-01), Yoneda
patent: 5312512 (1994-05-01), Allman et al.
Ackerman Stephan B.
Chartered Semiconductor Manufacturing Ltd.
Saadat Mahshid
Saile George O.
Szecsy Alek P.
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