Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
1999-01-20
2001-04-24
Whitehead, Jr., Carl (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S593000, C438S595000
Reexamination Certificate
active
06221744
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention in general relates to a method for forming a gate on a substrate in manufacturing semiconductor devices and more particularly, to a method for forming a gate with a controlled critical dimension and good gate oxide quality.
2. Description of the Related Art
In conventional method for forming a gate on a substrate in manufacturing semiconductor devices, large-grain polysilicon is employed as a gate material. Because the surface of the layer formed by the large-grain polysilicon is very rough due to the size of the grain of the polysilicon, deep UV exposure light is scattered when the polysilicon layer is patterned to form gates. In this case, the critical dimension of the gate is difficult to control, the uniformity thereof cannot be obtained and therefore, a kink effect occurs.
As a resolution of the above problem encountered in the conventional method, employment of amorphous silicon as a gate material on a substrate for manufacturing semiconductor devices is proposed. Since the surface of the layer formed by the amorphous silicon is smoother than that of large-grain polysilicon, a good critical dimension and uniformity of the gate can be obtained. However, in the subsequent thermal processes, the amorphous silicon re-crystallizes at an elevated temperature to form large-grain polysilicon in, for example, cylindrical shapes. Because of the thus-formed large-grain polysilicon, a channeling effect occurs at the interface between the polysilicon gate and the gate oxide layer. This results in penetration of conductive ions, for example N-type ion dopants or P-type ion dopants, and especially boron ions, through the large-grain polysilicon into the gate oxide.
Therefore, it is desired that a method be developed for forming a gate on a substrate, which method can control the critical dimension of the gate and uniformity thereof and simultaneously eliminate the channeling effect between the gate and gate oxide thereon.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for forming a gate on a substrate for manufacturing semiconductor devices to avoid the channeling effect at the interface between the gate oxide and the polysilicon layer.
It is another object of the present invention to provide a method for forming a gate with a controlled critical dimension and uniformity on a substrate for manufacturing semiconductor devices.
To achieve the above objects and other advantages of the present invention, a method for forming a gate on a substrate is described. The present method comprises the step of providing a gate oxide layer on top of a substrate. A polysilicon layer is overlaid on the gate oxide layer and next, an amorphous silicon layer is formed thereon. The amorphous silicon layer is defined to form a gate structure on gate oxide layer. Next, a thermal treatment is performed on the gate structure.
In accordance with one aspect of the present invention, a grain boundary exists between the polysilicon layer and the amorphous silicon layer so that the large-grain polysilicon having cylindrical shape is not formed at the elevated temperature necessary for the subsequent processes and thus, the channeling effect at the interface between the polysilicon gate and gate oxide on the substrate is avoided.
In accordance with another aspect of the present invention, a smooth top surface is provided by the amorphous silicon layer on the substrate, and the scattering of deep UV is thus avoided. Therefore, when defining the amorphous silicon layer to form a gate structure, the critical dimension of a gate is advantageously controlled and uniformity thereof can be obtained.
REFERENCES:
patent: 5710454 (1998-01-01), Wu
patent: 5767004 (1998-06-01), Balasubramanian et al.
patent: 5877074 (1999-03-01), Jeng et al.
Shih Hsueh-Hao
Wu Juan-Yuan
Yew Tri-Rung
Blakely & Sokoloff, Taylor & Zafman
Jr. Carl Whitehead
United Microelectronics Corp.
Vockrodt Jeff
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