Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-22
2001-02-06
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S589000, C438S593000
Reexamination Certificate
active
06184086
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the field of semiconductor manufacture, and more specifically to a floating gate memory device and a method for forming a floating gate memory device.
BACKGROUND OF THE INVENTION
A floating gate memory device such as an erasable programmable read-only memory (EPROM) includes an array of programmable and erasable memory cells. Typically, each memory cell comprises a single n-channel metal oxide semiconductor (NMOS) transistor, including a floating gate between a control gate and a channel. A bit of information is stored in each memory cell by storing a charge on the floating gate, to adjust a Vt (threshold voltage) of the transistor, which is the voltage that must be overcome by the gate to source voltage (Vgs) to activate the device.
For example, Vt for a typical transistor with no charge stored on its floating gate is approximately one to two volts. A voltage of at least one to two volts must be applied between the control gate and the source junction for the device to activate, that is, to allow current to flow through the device. If a charge is present on the floating gate Vt is effectively raised by the charge present. The net effect of this is that an intermediate voltage (a sense voltage) can be applied between the source and the control gate and if the transistor activates it is not programmed and if the transistor does not activate it is programmed.
The memory cells in the array are accessed via a plurality of column lines (digit lines) and a plurality of row lines (word lines). Each of the column lines is coupled to the drain of a corresponding memory cell transistor, and each of the row lines is coupled to a control gate of a corresponding memory cell transistor. The respective column and row lines are driven by address decoder and timing circuitry.
Several capacitances exist in an EPROM cell. The equation CC=C
1
/(C
1
+C
2
+C
3
+C
4
) describes these capacitances, where CC is the coupling coefficient, C
1
is the coupling between the floating gate and the control gate, C
2
is the coupling between the floating gate and the source, C
3
is the coupling between the floating gate and the drain, and C
4
is the coupling between the floating gate and the channel. As an example, if C
1
=0.5, C
2
=0.1, C
3
=0.1, and C
4
=0.3, the coupling coefficient would equal 0.5 (50%). If the area of the surface of the floating gate proximal to the control gate is increased by 100%, C
1
would increase to 1.0, and CC would increase to 0.67. With this increase, the size of the control gate and the floating gate could decrease by 50%, which would reduce the coupling coefficient by 17% back to the original 50%. As can be determined from the equation, the coupling coefficient can not reach the ideal state (1.00) since the capacitance between the floating gate and the control gate is always divided by itself plus some additional capacitance. Still, the goal of designers is to bring the coupling coefficient as close to unity as possible.
One problem associated with EPROMs is that two adjacent cells which share the same column line can interfere with each other electrically. For example, a cell can be slightly or “softly” erased or programmed when an adjacent cell has erasing or programming voltages applied to it because the two cells share their source and drain.
An EPROM cell which has an improved coupling coefficient, increased resistance to drain disturb between adjacent cells, and more efficient programming would be desirable.
SUMMARY OF THE INVENTION
A semiconductor device comprises a semiconductor layer having a trench therein, the trench having a bottom. The device further comprises a transistor source and a transistor drain separated by the trench, the source and the drain each having a lower surface. The trench bottom is below the lower surface of at least one of the source and the drain. A transistor channel runs along the bottom of the trench, and a floating gate is at least partially within the trench.
A method for forming a memory device comprises the steps of forming a transistor source having a lower surface and a transistor drain having a lower surface, the source and drain formed in a semiconductor substrate. A trench having a bottom is formed in the semiconductor substrate, the trench separating the source and drain. The trench is formed such that the bottom of the trench is below the lower surface of at least one of the source and drain. Next, a floating gate is formed at least partially within the trench.
Various objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.
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F.E. Holmes et al., “VMOS—A New MOS Integrated Circuit Technology”, 1974, Solid-State Electronics, pp. 791-797.
C.A.T. Salama, “A New Short Channel MOSFET Structure (UMOST)”, 1977, Solid State Electronics, pp. 1003-1009.
Micro)n Technology, Inc.
Trinh Michael
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