Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-03
2001-07-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S264000, C438S265000, C438S289000
Reexamination Certificate
active
06261906
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication processes, and more specifically to a method for forming a flash memory cell with improved drain erasure performance.
BACKGROUND OF THE INVENTION
Memory devices are one of the most important devices for storing of data and information. By storing data electrically in the memory devices, the data can be accessed with ultra high speed for various applications. The progress in memory device fabrication technology has made memory chips become a highly reliable and valuable device for a great amount of data reading and data writing access within an extremely short time. Various types of memories have been developed for a variety of applications like computation and communications systems.
An ideal storage device must have several characteristics. Numerous important applications of memory devices are specified with highly reliable and high speed operations. Low cost is needed for the explosively increasing demand on the more storage capability with a great number of storage units. High performance and high density are both important factors for performing reliable and high speed operations with least volume needed for the storage devices. Low power dissipation are highly demanded for providing longer operation time or greener operations especially for portable devices with limited capacity of power supply. Non-volatile or least refreshing characteristics is needed for both reliable, safety, and low power data storage.
Flash memory has became a valuable choice in the market of portable electrical devices and systems. High density and low power flash memories are required for future portable computer and telecommunication applications. The portable telecommunications and computing market has become a major driving force in semiconductor IC (Integrated Circuits) design and technology. The growing market requires low power, high density, and electrically programmable non-volatile memories, either embedded or stand-alone. Flash memory is another choice other than EEPROM (Electrically Erasable and Programmable ROM) because of its small size and improved reliability. Lots of new concepts and modifications about flash memory have been proposed to improve gate coupling of cells and result in faster data programming and erasure.
FIG. 1
illustrates a conventional split-gate flash memory cell in a cross-sectional view. A tunnel oxide layer
16
is formed on the substrate
2
that is uncovered by isolation regions
12
. The split-gate flash memory cell is formed on a substrate
2
having drain junction
4
therein. A control gate
6
is in the flash memory cell and communicates to an edge region of the drain junction
4
, or namely the diffused drain region, through a thin silicon oxide region
8
. Metal contacts
9
a
,
9
b
, and
9
c
are respectively formed to communicate with the source junction, control gate
6
, and drain junction
4
.
It is well known in the art that a doped region of silicon material will grow a thicker silicon oxide than undoped one in a thermal oxide growing process. In the conventional process flow of forming the split-gate flash memory cell, a field oxide is grown from the drain junction
4
in the step of thermally growing a thermal gate oxide under the center of the control gate
6
. Under the high dose of dopants in the drain junction
4
, a much thicker field oxide, which may be grown to as thick as 1000 angstroms, is formed. The field oxide is much thicker than what is expected for the thin silicon oxide region
8
and will significantly damage the operation performance of the flash memory cell.
When the split-gate flash memory cell is in operation, the field oxide, which enlarges the distance between the cell drain diffusion region and the control gate, will lower the erase efficiency of the flash memory cell. Moreover, since the formation of the thick field oxide will extend into the tunnel oxide region with its birds beak effect and damage the tunnel oxide quality, thus leads to cycling issue and reliability problems of the flash memory cell.
SUMMARY OF THE INVENTION
The present invention propose method for forming flash memory device. By the improved process flow and different pattern control in defining respective layers or regions, the flash memory cell is provided with improved drain erase performance. The prior art problem of field oxide under the control gate to damage the data erasure performance is eliminated.
The method for forming a flash memory cell mainly includes the steps as follows. At first, a semiconductor substrate having isolation regions thereon and having a well region provided between the isolation regions is provided. A tunnel oxide layer is formed on the well region and a first silicon layer is formed over the substrate. A dielectric layer is formed on the first silicon layer and a portion of the first silicon layer and the dielectric layer is removed to define a control gate opening within the first silicon layer on a portion of the well region.
Next, the substrate is doped in the region under the control gate opening to adjust a threshold voltage of the flash memory cell. A gate oxide layer is grown from the substrate in the control gate opening and a second silicon layer is formed on the substrate to fill within the control gate opening and to cover on the dielectric layer. The second silicon layer, the dielectric layer, and the first silicon layer are then patterned to form a gate structure of the flash memory cell, and to leave a drain opening exposing a portion of the tunnel oxide on the well region. Finally, the substrate is doped to form a drain region in the substrate between the gate structure and one of the isolation regions.
In the preferred embodiments, the dielectric layer comprises a tri-layer structure of a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer. Furthermore, the doping step for forming the drain region in the case includes at least two ion implantation steps to form a double diffused drain structure in the substrate, such as a phosphorus implantation at an energy between about 30 to 50 KeV to have a dose between about 1E14 to 5E14, and an arsenic implantation at an energy between about 40 to 60 KeV to have a dose between about 1E15 to 6E15.
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patent: 5352619 (1994-10-01), Hong
patent: 5635416 (1997-06-01), Chen et al.
patent: 5856224 (1999-01-01), Sheu
patent: 5963808 (1999-10-01), Lu et al.
patent: 5981341 (1999-11-01), Kim et al.
patent: 6133097 (2000-10-01), Hsieh et al.
patent: 6168995 (2001-01-01), Kelley et al.
Chen Chih-Ming
Hsu Cheng-Yuan
Bowers Charles
Smoot Stephen W.
Worldwide Semiconductor Manufacturing Corp.
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