Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-27
2003-04-08
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S271000
Reexamination Certificate
active
06544844
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to non-volatile digital memory, and more particularly, to FLASH EPROM memory technology incorporating floating gates having reduced lateral dimensions.
2. Description of Related Art
FLASH EPROM memory is a class of non-volatile storage integrated circuits. In general, FLASH EPROMS have the capability of electrically erasing, programming, or reading a memory cell on a chip. Generally, a FLASH EPROM includes a floating gate and a control gate which form an electrical connection. A FLASH EPROM operates by charging or discharging electrons in the floating gate of the memory cell in a capacitative manner. The floating gate is formed of a conductive material, typically made of polysilicon, which is insulated from the channel of the transistor by a layer of oxide or other insulating material, and insulated from the control gate or word-line of the transistor by a second layer of insulating material.
The act of charging the floating gate is termed a “program” step for a FLASH EPROM. The program step may be accomplished through so-called hot electron injection by establishing a large positive voltage between the control gate and the source. The act of discharging the floating gate is called the “erase” function for a FLASH EPROM. The erase function is typically carried out by an F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase).
Due to increasing memory demands, a need exists to further reduce the size of memory devices, such as FLASH EPROMs. Reducing the cell size of memory devices increases performance and reduces power consumption.
Several devices have been developed with reduced cell size. One such device is described in “A Low Voltage Operating Flash Memory Cell with High Coupling Ratio Using Homed Floating Gate with Fine HSG,” by Kitamura et al., 1998 Symposium on VLSI Technology Digest of Technical Papers. Another example of a memory device with reduced cell size is described in “A 0.24-&mgr;m Cell Process With 0.18-&mgr;m Width Isolation and 3D Interpoly Dielectric Films for 1-GB Flash Memories” by Kobayashi et al., IEEE 97-275 (1997).
Reducing the size of a memory cell has lead to memory cells with certain disadvantages including overbearing floating gates, or intermediate structures formed during the manufacturing of the floating gate, which degrade the tunnel oxide layer. The formation of sharp corners on the floating gate also leads to charge leakage.
SUMMARY OF THE INVENTION
A floating gate for use in a memory cell is provided which comprises a first end region adjacent a first lateral end of the floating gate; and a middle region positioned laterally toward a middle of the floating gate relative to the first end region, the middle region having a vertical thickness which is less than a vertical thickness of the first end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first end region and middle region by one or more subsequent fabrication steps.
In one variation, the first end region and the middle region have top surfaces which are substantially parallel to a plane of a substrate underlying the floating gate, the top surfaces of the first end region and middle region being connected to one another by a surface which is substantially perpendicular to the plane of the substrate underlying the floating gate.
In another variation, the floating gate further includes a first sloped region positioned between the first end region and the middle region. The first sloped region may be shaped to have a top surface which is positioned at an angle between about 0 and 45 degrees relative to a line perpendicular to a plane of a substrate underlying the floating gate.
A floating gate for use in a memory cell is also provided which comprises a first end region adjacent a first lateral end of the floating gate; a second end region adjacent a second lateral end of the floating gate opposite the first lateral end; and a middle region positioned laterally between the first and second end regions, the middle region having a vertical thickness which is less than a vertical thickness of the first end region and which is less than a vertical thickness of the second end region; wherein the floating gate is composed of a material which is formed during a single fabrication step and shaped to form the first and second end regions and middle region by one or more subsequent fabrication steps.
In one variation, the first and second end regions and the middle region have top surfaces which are substantially parallel to a plane of a substrate underlying the floating gate, the top surfaces of the first end region and middle region are connected to one another by a surface which is substantially perpendicular to the plane of the substrate underlying the floating gate and the top surfaces of the second end region and middle region are connected to one another by a surface which is substantially perpendicular to the plane of the substrate underlying the floating gate.
In another variation, the floating gate further includes a first sloped region positioned between the first end region and the middle region and a second sloped region positioned between the second end region and the middle region. The first and second sloped regions may be shaped to have top surfaces which are positioned at an angle between about 0 and 45 degrees relative to a line perpendicular to a plane of a substrate underlying the floating gate.
According to the above embodiments, the first and second end regions and the middle region may have top surfaces which are substantially planar. The first and second end regions and middle regions may also have top surfaces which are substantially parallel to a plane of a substrate underlying the floating gate.
Also according to the above embodiments, the floating gate preferably has a bottom surface facing a plane of a substrate underlying the floating gate, the floating gate being positioned substantially within a lateral footprint defined by the bottom surface of the floating gate.
Also according to the above embodiments, the first end region, middle region and second end region combined have a width of less than one micron, and preferably less than about 0.5 micron.
In regard to each of the above floating gate embodiments, the floating gate may be incorporated into a floating gate memory cell comprising: a substrate; source and drain regions positioned over the substrate; an insulating layer positioned over the source and drain regions; the floating gate positioned over the insulating layer between the source and drain regions; and a control gate positioned over the dielectric insulator.
Also provided according to the present invention are methods for fabricating the floating gates of the present invention. According to one embodiment, a method is provided for forming a contoured floating gate for use in a floating gate memory cell the method including forming a floating gate comprising a polysilicon layer over a substrate; forming oxide layers on opposing sides of the floating gate, the oxide layer having a vertical thickness greater than a vertical thickness of the floating gate; forming a spacer layer over the oxide layers and the floating gate; removing a portion of the spacer layer such that side walls leave a top surface of the floating gate positioned laterally toward a middle region of the floating gate is exposed; and removing a portion of the floating gate underlying the exposed top surface of the middle region to form the contoured floating gate.
In one variation of the method, the floating gate includes a first end region at a first lateral end of the floating gate and a second end region at a second lateral end of the floating gate, where the spacer layer formed during the step of forming the spacer layer has a vertical thickness at the first end region and a vertical thickness at the second end region
Chang Yun
Huang Chin-Yi
Beffel, Jr. Ernest J.
Haynes Beffel & Wolfeld LLP
Macronix International Co. Ltd.
Nhu David
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