Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2006-10-17
2006-10-17
Lee, Hsien-Ming (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S296000, C438S424000, C257S510000
Reexamination Certificate
active
07122416
ABSTRACT:
A method for forming an isolation filled trench (25) in a silicon layer (21) of an SOI structure (20). The trench (25) is relieved adjacent its open mouth (30) in order to displace the commencement of bridging of the trench (25) with the filling material, to a level (36) well below a first surface (27) of the silicon layer (21) for in turn displacing voids (35) from the open mouth (30) into the trench (25) below the level (36). The trench may be relieved by forming tapered portions (40) in the side wells (29) adjacent the open mouth (30), and/or by relieving one or more lining layers (32) in the trench (25) adjacent the open mouth (30) to form tapered portion (52) and (53). Instead of relieving the trench (25) by tapering the side walls (29) relieving recesses may be formed into the first surface (27) of the silicon layer (21) adjacent the open mouth (30). By relieving the trench (25) or one or more of the lining layers (32) adjacent the open mouth (30) the commencement of bridging of the trench with the filling material is displaced downwardly to a level (36), which displaces voids formed in the trench below the level (36). By sufficiently relieving the trench (25) and/or lining layers (32) adjacent the open mouth to a sufficient depth the formation of voids in the trench may be completely avoided.
REFERENCES:
patent: 4639288 (1987-01-01), Price et al.
patent: 4656730 (1987-04-01), Lynch et al.
patent: 4839306 (1989-06-01), Wakamatsu
patent: 6081662 (2000-06-01), Murakami et al.
patent: 6180493 (2001-01-01), Chu
patent: 6198150 (2001-03-01), Gelzinis
patent: 6468853 (2002-10-01), Balasubramanian et al.
patent: 6544861 (2003-04-01), Joo
patent: 6627514 (2003-09-01), Park et al.
patent: 6812115 (2004-11-01), Wieczorek et al.
patent: 2001/0023134 (2001-09-01), Akatsu et al.
patent: 2001/0045614 (2001-11-01), Begley et al.
patent: 2002/0121673 (2002-09-01), Jono et al.
patent: 2004/0102005 (2004-05-01), Dong et al.
patent: 2004/0198038 (2004-10-01), Huang et al.
patent: 0 048 175 (1981-09-01), None
Gormley Colin Stephen
Nevin William Andrew
Analog Devices Inc.
Gauthier & Connors LLP
Lee Hsien-Ming
LandOfFree
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