Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-01
2002-04-30
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000
Reexamination Certificate
active
06380039
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to the fabrication process of semiconductor devices, particularly field effect transistors (FET's) comprising L-shaped insulating spacers. These spacers are of particular interest for fabricating FET's with a sub 0.25 &mgr;m channel length.
BACKGROUND OF THE INVENTION
Insulating spacers are widely used in the process of manufacturing integrated circuits. These spacers are mainly used for two important applications namely to isolate two conductive patterns one from another and as masking elements. Especially if their sole function is their use as masking elements, disposable spacers are often used. Disposable spacers are spacers which are removed later on in the process. However, for quite a number of applications permanent spacers are used because both their function as insulating elements as well as masking element is required. Examples of such permanent spacers can be found, e.g. in a FET, particularly in a FET with a lightly doped drain (LDD) and/or source, where the spacers are located at the sidewalls of the gate and are used to isolate the gate from the drain and/or source as well as to serve as a masking elements for the implantation of the highly doped drain/source regions. The formation of the (permanent) spacers is a very critical part of the manufacturing process because this spacer formation has a large influence on the definition of the intrinsic device and therefore on the device characteristics. Because the dimensions of the intrinsic device are very small, i.e. typically in the deep sub-micron range, one has to be able to define these spacers in a very controllable and reproducible way in order to be able to meet the stringent yield and reliability specifications. This problem will even be more stringent in the future due to the ongoing downscaling of the device dimensions.
In the past so-called lightly doped drain devices (LDD devices) have been introduced mainly to guarantee the specified operation during lifetime for a given supply voltage. This can be accomplished due to the electrical field lowering effect of lightly doped extensions. The major problems of such devices are:
establishing a well-defined and controllable overlap between the gate and the lightly doped source and drain extensions
establishing a well-defined and controllable offset between the lightly doped extensions and the respective (highly) doped source/drain regions in order to achieve a less steep doping gradient as compared with devices without extensions and thus a lower electrical field.
Conventionally the solution proposed to solve the overlap problem was either by means of out-diffusion of the as implanted lightly doped extensions (which were implanted self-aligned to the gate), or by means of LATID, where an implant under a large tilt angle is performed. To define an (extra) offset between the extensions and the respective source/drain regions, spacers adjacent to the gate of the device were used, i.e. lightly doped extensions were implanted self-aligned to the gate before the spacer formation, while the highly doped regions were implanted using the spacer as a mask. In the latter case contrary to the dimensions of the spacer, the precise shape of the spacer is not that important regarding the functionality of the device as long as the spacer isolates the gate from the drain/source regions and blocks the highly doped source/drain implantation. Remark that this conventional method requires two separate implantation steps and lithographic steps in order to form the source/drain regions, i.e. the highly doped regions as well as the extensions. Furthermore because the LDD implantation to form the extensions is in such an early stage of the process, the extensions are subjected to a large thermal budget.
Concerning sub 0.25 &mgr;m CMOS and BiCMOS process generations, it is not likely that lightly doped extensions will still be required in field effect transistors in order to guarantee the specified operation during lifetime for a given supply voltage, due to the downscaling of the supply voltage. Hot carrier degradation is no longer a big issue, especially not for p-channel devices. However, the fabrication of shallow junctions, a low contact resistance to these junctions using silicide layers and a well defined and controllable gate overlap will be issues in these sub 0.25 &mgr;m devices. Particularly because in se in conventional device concepts shallow junctions and a stable, reliable silicidation process are difficult to combine often resulting in a very limited process window.
The U.S. Pat. No. 5,702,986 is related to a process of forming L-shaped spacers and a process of forming LDD FET's comprising such spacers. The L-shaped spacers are primarily introduced to limit mechanical stress. The spacer formation process of U.S. Pat. No. 5,702,986 is however a complicated process comprising dry and wet etching steps. Another disadvantage of this process is that the anisotropic spacer etch stops on/in the silicon substrate.
SUMMARY OF THE INVENTION
In an aspect of the invention, a scaleable device concept and a method for fabrication thereof is disclosed, which allows for a minimal well-controlled gate overlap by using low resistivity source/drain extension regions with shallow junctions. On the other hand, these new device concepts of the present invention facilitate the silicidation process because deeper source/drain contact regions can be used without influencing the gate overlap due to the fact that the gate overlap is defined by the extension regions and not by the source/drain contact regions. So, according to this aspect of the invention, a method for fabricating a field effect transistor on a substrate is disclosed, said substrate comprising at least one first part and at least one second part adjacent to said first part, said first part being covered with at least one first insulating layer and at least one conductive layer thereby forming a first area, i.e. e.g. the gate area of a FET, said second part being either uncovered or covered with said first insulating layer, thereby forming a second area, said method comprising the steps of:
a) forming a second insulating layer on said first and said second area, at least when said second part of said substrate is uncovered;
b) forming a third insulating layer on said second insulating layer or on said first and second area;
c) forming a disposable layer on said third insulating layer;
d) anisotropically etching said disposable layer using said third insulating layer as an etch stop layer to thereby form at least one spacer of said disposable layer on said second area adjacent to said first area;
e) removing said third insulating layer, using said spacer of said disposable layer as a mask;
f) removing said spacer of said disposable layer to thereby free the insulating spacer formed in said third insulating layer, said insulating spacer comprising a first portion being the base of said spacer, and a second portion, being the upright part of the insulating spacer adjacent to said first area; and
g) performing a source/drain dopant implantation using said first portion of said insulating spacer as a an element to lower the penetration depth of said implantation in said substrate thereby assuring that substantially the entire implantation dose penetrates at least into the part of the substrate below said first portion of said spacer. In other words, at least the extension regions are defined. Preferably, the insulating spacer formed is “L”-shaped.
In an embodiment of the invention, prior to the source/drain implantation, the first and the second insulating layer are removed using the insulating spacer formed in the third insulating layer as a mask.
In another embodiment of the invention a method is disclosed wherein said disposable layer is a silicon layer, e.g. a polysilicon or an amorphous silicon layer and wherein eventually, prior to the dry etching of said silicon layer, i.e. step d), first a native oxide, formed during exposure of said substrate to an ambient co
Badenes Goncal
Beckx Stephan
Deferm Ludo
Vanhaelemeersch Serge
Chaudhuri Olik
Interuniversitair Microelektronica Centrum (IMEC VZW)
Knobbe Martens Olson and Bear LLP
Pham Hoai
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