Method for forming a ferroelectric capacitor under the bit line

Details Method for forming a ferroelectric capacitor under the bit line Method for forming a ferroelectric capacitor under the bit line

1999-01-27

2001-07-03

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S003000, C438S253000, C438S396000, C257S295000, C257S306000

Reexamination Certificate

active

06255157

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to ferroelectric dielectrics and more specifically to a ferroelectric capacitor that is annealed before the bitline is formed and which is formed over the active area to reduce the size of the memory cell.
2. Description of the Related Art
Ferroelectric dielectrics are being actively investigated for use in a non-volatile memory devices and high-dielectric materials are being actively investigated for use in DRAM (Dynamic Random Access Memory) devices. In such devices, a capacitor is fabricated by depositing a thin film of a ferroelectric material such as SrBi
2
Ta
2
O
9
(SBT),Pb(Zr,Ta)O
3
(lead zirronate titanate), or their many variations, or a high-dielectric material such as (Ba,Sr)TiO
3
(KST) between 2 electrodes. The electrodes are either noble metals (Ir, Pt, Ru, Pd, Au) or noble metal oxides (RuO
2
,IrO
2
, . . . ). In the completed device, one electrode is connected to a transfer device while the other electrode serves as a common reference plate or a drive line.
More specifically,
FIG. 1
illustrates an N-type substrate
10
having a N+ diffusion region
11
, an insulating layer
12
and a polysilicon plug
13
within the insulating layer
12
. Further, the structure shown and
FIG. 1
includes a barrier layer
14
, top and bottom electrodes
15
, the ferroelectric l
6
and an insulator
17
.
FIG. 2
illustrates a bit line
20
, a word line
21
, a tungsten plug
22
, a top electrode
23
and a bottom electrode
24
on either side of a ferroelectric
25
. The tungsten plug
22
is connected to the top electrode
23
by a local interconnect
26
.
One problem that occurs when fabricating such conventional devices is the high temperature anneal required to form the correct phase of the ferroelectric dielectric. This anneal typically requires a temperature of 700-850° C. in an oxidizing ambient. Since the noble metal or noble metal oxide electrodes are not good diffusion barriers for oxygen, any conductor connected to the electrode will have a tendency to be oxidized during this anneal. Therefore, such conventional structures are very difficult to produce and have a high defect rate associated with the high-temperature anneal.
For example, with the structure shown in
FIG. 1
, the conductor
13
is below the ferroelectric
16
and must be formed before the ferroelectric
16
. Therefore, during the anneal of the ferroelectric the conductor
13
may be oxidized, which reduces the electrical conductivity between the electrodes
15
and the conductor
13
, decreases device performance and increases defect rates.
While the local interconnect
26
shown in
FIG. 2
is positioned above the top electrode
23
and can be formed after the ferroelectric
25
is annealed, the capacitor
25
is not formed over the device
21
resulting in a large cell size.
The invention overcomes the foregoing problems by forming the ferroelectric in a processed which avoids oxidation of the conductive paths to the electrodes of the ferroelectric capacitor, and still provides a small cell size, as discussed in greater detail below.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for forming an integrated circuit structure including forming at least one transistor structure, forming at least one ferroelectric capacitor above the transistor structure, annealing the ferroelectric capacitor, and forming at least one contact line between the transistor structure and the ferroelectric capacitor.
The forming of the ferroelectric capacitor includes depositing an insulator above the transistor structure, depositing a lower electrode above the insulator, depositing a ferroelectric material above the lower electrode, and depositing an upper electrode above the ferroelectric material. Before the depositing of the ferroelectric material, a portion of the lower electrode above the transistor structure is removed so as to form a recess in the ferroelectric material and the upper electrode.
Contact line openings are formed through the ferroelectric capacitor and insulating spacers are formed in the contact line openings above the lower electrode to insulate the ferroelectric material and the upper electrode from the contact line and to allow the lower electrode to contact the contact line. Further, there is an insulator formed above the ferroelectric capacitor. The ferroelectric material comprises SrBi
2
Ta
2
O
9
(SBT), or its may variations, or Pb(Zr,Ti)O
3
, (PZT), or its many variations, or a high-dielectric material such as (Ba, Sr)TiO
3
(KST).
The contact plug electrically connects a diffusion region of the transistor and a lower electrode of the ferroelectric capacitor.
The invention does not suffer the problem of conventional structures, discussed in the Background section, in that the bitline will not be oxidized during the anneal of the ferroelectric material because the ferroelectric material is annealed before the deposition of the bitline material.
Further, the invention produces a structure wherein the ferroelectric capacitor is formed directly above the transistor structure. The structure is extremely economical with space and reduces the overall size of the integrated circuit device.


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T. Yamazaki, et al., “Advanced 0.5&mgr;m FRAM Device Technology with Full Compatibility . . . ”, IEDM, 1997, pp. 613-616.

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