Method for forming a dual metal gate structure

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S195000, C438S197000, C438S275000, C438S283000, C257SE21637

Reexamination Certificate

active

07666730

ABSTRACT:
A method for forming a semiconductor structure includes forming a channel region layer over a semiconductor layer where the semiconductor layer includes a first and a second well region, forming a protection layer over the channel region layer, forming a first gate dielectric layer over the first well region, forming a first metal gate electrode layer over the first gate dielectric, removing the protection layer, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer over the second gate dielectric layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and the first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and the second metal gate electrode layer over the channel region layer.

REFERENCES:
patent: 6645818 (2003-11-01), Sing et al.
patent: 6794252 (2004-09-01), Rotondaro et al.
patent: 6897095 (2005-05-01), Adetutu et al.
patent: 7344934 (2008-03-01), Li
patent: 7445981 (2008-11-01), Karve et al.
patent: 2006/0157796 (2006-07-01), Kim et al.
patent: 2007/0111453 (2007-05-01), Lee et al.
patent: 2007/0152276 (2007-07-01), Arnold et al.
patent: 2007/0278590 (2007-12-01), Zhu et al.
patent: 2008/0220603 (2008-09-01), Fukushima et al.
patent: 2008/0280404 (2008-11-01), Chudzik et al.
patent: 2009/0218632 (2009-09-01), Cheng
patent: 2004-095527 (2004-11-01), None
PCT/US2008/064192 International Search Report and Written Opinion, Nov. 26, 2008.
Song, S.C. et al.; “Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-K and Dual Metal Gate CMOS Integration”; 2006 Symposium on VLSI Technology Digest of Technical Papers; 2006; 2 pages; IEEE.
Harris, H. Rusty et al.; “Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme”; 2007; pp. 154-155; 2007 Symposium on VLSI Technology Digest of Technical Papers.
U.S. Appl. No. 11/559,633, filed Nov. 14, 2006.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming a dual metal gate structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming a dual metal gate structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming a dual metal gate structure will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4178841

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.