Method for forming a dual metal gate structure

Details Method for forming a dual metal gate structure Method for forming a dual metal gate structure

2007-06-29

2008-11-04

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S369000

Reexamination Certificate

active

07445981

ABSTRACT:
A method includes forming a first gate dielectric layer over a semiconductor layer having a first and a second well region, forming a first metal gate electrode layer over the first gate dielectric, forming a sidewall protection layer over the first metal gate electrode layer and adjacent sidewalls of the first gate dielectric layer and first metal gate electrode layer, forming a channel region layer over the second well region, forming a second gate dielectric layer over the channel region layer, forming a second metal gate electrode layer, and forming a first gate stack including a portion of each of the first gate dielectric layer and first metal gate electrode layer over the first well region and forming a second gate stack including a portion of each of the second gate dielectric layer and second metal gate electrode layer over the channel region layer and over the second well region.

REFERENCES:
patent: 6645818 (2003-11-01), Sing et al.
patent: 6897095 (2005-05-01), Adetutu et al.
Song, S.C. et al.; “Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-K and Dual Metal Gate CMOS Integration”; 2006 Symposium on VLSI Technology Digest of Technical Papers; 2006; 2 pages; IEEE.
Harris, H. Rusty et al.; “Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme”; 2007; pp. 154-155; 2007 Symposium on VLSI Technology Digest of Technical Papers.
U.S. Appl. No. 11/559,633, filed Nov. 14, 2006.

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