Method for forming a DRAM cell with a ragged polysilicon crown-s

Details Method for forming a DRAM cell with a ragged polysilicon crown-s Method for forming a DRAM cell with a ragged polysilicon crown-s

1997-11-03

1998-06-16

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438254, 438398, H01L 218242, H01L 2120

Patent

active

057669953

ABSTRACT:
A method for forming a ragged polysilicon crown-shaped capacitor of a dynamic random access memory cell is disclosed. The method includes forming a first dielectric layer (122) on a semiconductor substrate, and then forming a first silicon nitride layer (124) on the first dielectric layer. Next, a portion of the first silicon nitride layer is removed to form a first hole therein. A first polysilicon spacer (126) is then formed on sidewall of the first silicon nitride layer. Portions of the first dielectric layer are etched, therefore exposing a surface of the substrate, and forming a second hole in the first dielectric layer. Subsequently, a second doped polysilicon layer (128) is formed, thereby refilling the second hole. A second silicon nitride layer (130) is then formed, and the second silicon nitride layer and the second doped polysilicon layer are patterned to form a storage node. After patterning to form a third doped polysilicon spacer (132) on sidewalls of the second silicon nitride layer and the second doped polysilicon layer, the second silicon nitride layer and the first silicon nitride layer are etched by phosphoric acid solution (H.sub.3 PO.sub.4), and therefore surfaces of the third doped polysilicon spacer and the second doped polysilicon layer are roughened. Finally, a second dielectric layer (136) is formed, and a conductive layer (138) is formed on the second dielectric layer.

REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5164337 (1992-11-01), Ogawa et al.
patent: 5266514 (1993-11-01), Tuan et al.
Watanabe, H. et al, "A New Cylindrical Capacitor Using Hemispherical Grained Si(HSG-Si) for 256Mb DRAMs", IEDM, 1992, pp. 259-262.
Sakao, M. et al, "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs", IEDM, 1990, pp. 655-658.
Watanabe, H. et al, "A Novel Stacked Capacitor with Porous-Si Electrodes for High Density DRAMs", pp. 17-18, NEC Corp. Japan, Publisher and Publishing date are unknown.

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