Method for forming a DRAM cell and array to store two-bit data

Details Method for forming a DRAM cell and array to store two-bit data Method for forming a DRAM cell and array to store two-bit data

1998-02-04

1999-06-01

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438253, H01L 218242

Patent

active

059096195

ABSTRACT:
A DRAM cell capable of storing two bits of digital data as four levels of stored charge within the DRAM cell is disclosed. The four level DRAM cell has a pass transistor, a trench capacitor, and a stack capacitor. The pass transistors has a source connected to a bit line voltage generator to control placement of the charge within the four level DRAM cell, a gate connected to a word line voltage generator to control activation of the DRAM cells, and a drain. The trench capacitor has a top plate connected to the drain and a bottom plate connected to a substrate biasing voltage source. The stack capacitor has a first plate connected to the drain and a second plate connected to a coupling-gate voltage generator. The coupling-gate voltage generator will provide four levels of voltage that will indicate the level of charge to be stored within the four level DRAM cell. An interconnecting block that will interconnect the top plate of the trench capacitor to the first plate of the stack capacitor. The interconnection point between the trench capacitor and the stack capacitor will form the storage node that will retain the level of charge that indicates the state of the two bits of digital data. Four level DRAM cells will be arranged in a plurality of rows and columns to form an array of four level DRAM cells.

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"The Evolution of DRAM Cell Technology", El-Kareh et al, Solid State Technology, May 1997, pp. 89-101.

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