Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-16
2001-07-24
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S253000, C438S396000
Reexamination Certificate
active
06265263
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to dynamic random access memory (DRAM) fabrication, and more particularly, to a method for forming a DRAM capacitor with porous storage node and rugged sidewalls.
2. Description of the Prior Art
The increasing popularity of electronic equipment, such as computers for example, is increasing the demand for large semiconductor memories.
FIG. 1
shows a simplified diagram of the organization of a typical large semiconductor memory
14
. The storage cells of the memory
14
are arranged to an array including horizontal rows and vertical columns. The horizontal lines connected to all of the cells in the row are referred to as word lines
11
, and the vertical lines connected to all of the cells in the column are referred to as bit lines
13
. Data flow into and out of the cells via the bit lines
13
.
Row address
10
and column address
12
are used to identify a location in the memory
14
. A row address buffer
15
and a column address buffer
17
, respectively, receive row address
10
signals and column address
12
signals. The buffers
15
and
17
then drive these signals to a row decoder
16
and column decoder
18
, respectively. The row decoder
16
and the column decoder
18
then select the appropriate word line and bit line corresponding to the received address signal. The word and bit lines select a particular memory cell of the memory
14
corresponding to the received address signals. As is known in the art of semiconductor memory fabrication, the row decoder
16
and the column decoder
18
reduce the number of address lines needed for accessing a large number of storage cells in the memory
14
.
The array configuration of semiconductor memory
14
lends itself well to the regular structure preferred in “very large scale integration ” (VLSI) or “ultra large scale integration (ULSI) ICs. For example, the memory
14
can be a dynamic random access memory (DRAM). The DRAM has become one of the most widely used types of semiconductor memory due to its low cost per bit, high device density and flexibility of use concerning reading and writing operations.
Early DRAMs used storage cells each consisting of three transistors and were manufactured using P type channel metal-oxide-semiconductor (PMOS) technology. Later, a DRAM storage cell structure consisting of one transistor and one capacitor was developed. A circuit schematic diagram corresponding to this structure is shown in FIG.
2
A. The gate of the transistor
20
is controlled by a word line signal, and data, represented by the logic level of a capacitor voltage, is written into or read out of the capacitor
22
through a bit line.
FIG. 2B
shows the cross section of a traditional one-transistor DRAM storage cell that uses a polysilicon layer
24
as one plate of the capacitor. The substrate region under the polysilicon plate
24
serves as the other capacitor electrode. A voltage can be applied to the plate
24
to store a logic value into the capacitor.
As the semiconductor memory device becomes more highly integrated, the area occupied by a capacitor of a DRAM storage cell typically shrinks. Thus, the capacitance of the capacitor is reduced owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise ratio in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, thereby achieving both high cell integration and reliable operation.
One approach for increasing the capacitance while maintaining the high integration of the storage cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing the capacitor electrodes may have protrusions, fins, cavities, etc., to increase the surface area of the capacitor electrode, thereby increasing the storage capacitance while maintaining the small area occupied on the substrate surface. Consequently, this type of capacitor has come to be widely used in DRAM devices.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for forming a porous storage node with rugged sidewalls for a dynamic random access memory cell that substantially increases the surface area of the capacitor.
In the preferred embodiment of the present invention, a first dielectric layer is firstly formed on a semiconductor substrate, followed by the formation of a second dielectric layer on the first dielectric layer, and the formation of a third dielectric layer on the second dielectric layer. Next, the first, second, and third dielectric layers are patterned to form a contact hole therein. A doped polysilicon layer is then formed within the contact hole and over the third dielectric layer, followed by the formation of a fourth dielectric layer over the doped polysilicon layer. A patterning step patterns the fourth dielectric layer and the doped polysilicon layer to define a storage node. A hemispherical grained silicon layer is then formed on the fourth dielectric layer, on sidewalls of the storage node, and on the third dielectric layer. The hemispherical grained silicon layer is etched to define a plurality of cavities between grains of the hemispherical grained silicon layer and to expose the fourth dielectric layer through the plurality of cavities. The fourth dielectric layer and the doped polysilicon layer underlying the cavities are then etched to form a porous storage node. The fourth dielectric layer and the third dielectric layer are removed, followed by the formation of a fifth dielectric layer on the porous storage node and the substrate. Finally, a conductive layer is formed on the fifth dielectric layer.
REFERENCES:
patent: 5213992 (1993-05-01), Lu
patent: 5342800 (1994-08-01), Jun
patent: 5350707 (1994-09-01), Ko et al.
patent: 5480824 (1996-01-01), Jun
patent: 5616511 (1997-04-01), Hirota
patent: 5670405 (1997-09-01), Tseng
patent: 5766995 (1998-06-01), Wu
patent: 5789290 (1998-08-01), Sun
patent: 5795806 (1998-08-01), Tseng
patent: 5817554 (1998-10-01), Tseng
patent: 5869368 (1999-02-01), Yew et al.
patent: 5981336 (1999-11-01), Chern
patent: 6051464 (2000-04-01), Chen et al.
patent: 02000114472 (2000-04-01), None
Bowers Charles
Kebede Brook
Texas Instruments - Acer Incorporated
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