method for forming a DRAM capacitor using HSG-Si technique and o

Details method for forming a DRAM capacitor using HSG-Si technique and o method for forming a DRAM capacitor using HSG-Si technique and o

1997-02-28

1998-09-08

Chang, Joni

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438255, 438398, H01L 218242, H01L 2120

Patent

active

058044809

ABSTRACT:
A method for forming a DRAM capacitor using a HSG-Si includes forming a dielectric layer over a substrate. A polysilicon layer is formed over the dielectric layer, and a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process. The HSG-Si layer includes a large number of silicon grains spaced apart on the surface of the polysilicon layer with the area of the polysilicon layer's surface being left exposed. Next, oxygen is implanted into the polysilicon layer using the silicon grains as an implant mask, thereby forming oxygen regions in the polysilicon layer. The HSG-Si layer is removed and the oxygen regions are annealed to transform the atom regions into oxide regions. Afterwards, the polysilicon layer is etched using the oxide regions as an etching mask, thereby forming a large number of trenches in the polysilicon layer. The oxide regions and portions of the polysilicon layer are removed to form a storage node, which serves as a bottom electrode of the DRAM cell capacitor.

REFERENCES:
patent: 5256587 (1993-10-01), Jun et al.
patent: 5302540 (1994-04-01), Ko et al.
H. Arima, et al., "A Novel Stacked Capacitor with Dual Cell Plate for 64Mb DRAMs", 1990 IEDM, pp. 651-654, (1990).
M. Sakao, et al., "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs", 1990 IEDM, pp. 655-658, (1990).
H. Watanabe, et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs", 1990 IEDM, pp. 259-262, (1990).

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