Method for forming a DRAM capacitor using HSG-Si

Details Method for forming a DRAM capacitor using HSG-Si Method for forming a DRAM capacitor using HSG-Si

1997-02-28

1998-06-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438766, H01L 218242

Patent

active

057598940

ABSTRACT:
A method for forming a DRAM capacitor using HSG-Si includes forming a dielectric layer over a substrate. A portion of the dielectric layer is removed to expose a contact area on the substrate. A polysilicon layer is then formed over the dielectric layer and in the first trench. Then, a hemispherical-grained silicon (HSG-Si) layer is formed on the polysilicon layer using an initial phase HSG-Si process, thereby forming a large number of silicon grains on the polysilicon layer. Next, nitrogen atoms are implanted into the polysilicon layer using the HSG-Si layer as a mask to form nitrogen regions in the polysilicon layer. The HSG-Si layer is then removed and the polysilicon layer is thermally oxidized. The nitrogen regions function as an anti-oxidation mask so that polysilicon-oxide regions are formed between the nitrogen regions in the polysilicon layer. Afterwards, an etching process is performed using the polysilicon-oxide regions as a mask so that the nitrogen regions and portions of the polysilicon layer beneath the nitrogen regions are removed. This etching step forms second trenches in the polysilicon layer between the polysilicon-oxide regions, which are subsequently removed. After removing the polysilicon-oxide regions, the polysilicon layer is patterned and etched to form a bottom electrode of the capacitor of the dynamic random access memory. The capacitor dielectric and the top electrode of the capacitor are then formed using conventional methods.

REFERENCES:
patent: 5213992 (1993-05-01), Lu
patent: 5302540 (1994-04-01), Ko et al.
patent: 5464791 (1995-11-01), Hirota
H. Arima, et al., "A Novel Stacked Capacitor with Dual Cell Plate for 64Mb DRAMs", 1990 IEDM, pp. 651-654, (1990).
M. Sakao, et al., "A Capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64Mb DRAMs", 1990 IEDM, pp. 655-658, (1990).
H. Watanabe, et al., "A New Cylindrical Capacitor Using Hemispherical Grained Si (HSG-Si) for 256Mb DRAMs", 1990 IEDM, pp. 259-262, (1990).

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