Method for forming a DRAM capacitor

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

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438254, 438397, H01L 218242

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active

058375759

ABSTRACT:
An improved method for forming a dynamic random access memory (DRAM) cell capacitor with increased capacitance is disclosed. The method includes forming a planarized dielectric layer on a semiconductor substrate. Then a minimum dimension trench is formed to expose the source region of the DRAM cell MOSFET, thereby forming the node contact for the bottom storage node of the DRAM cell capacitor. A thick doped polysilicon layer is then formed over the dielectric layer, filling the trench. A nitride layer is formed on the dielectric layer. Thereafter, a photoresist layer is formed on the silicon nitride layer and patterned to form a minimum dimension mask aligned with the polysilicon filled trench in the dielectric layer. The photoresist mask is then etched, causing the photoresist mask to be narrower than the minimum dimension. The silicon nitride layer is then anisotropically etched to expose the polysilicon layer. After stripping the photoresist mask, a silicon nitride mask is formed on the polysilicon layer. A polysilicon-oxide layer is then grown by thermal oxidation. The silicon nitride mask is then removed, leaving a portion of the polysilicon layer exposed. The polysilicon layer is then etched using the polysilicon-oxide layer as a mask, thereby forming a deep trench that is narrower than the minimum dimension. The polysilicon-oxide layer is removed to expose the polysilicon layer. The polysilicon layer is then patterned and etched to removed the polysilicon layer around the trench. The resulting polysilicon structure forms a bottom electrode of the DRAM cell capacitor.

REFERENCES:
patent: 5429980 (1995-07-01), Yang et al.
patent: 5521112 (1996-05-01), Tseng
patent: 5712182 (1998-01-01), Madan

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