Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-10
2004-12-28
Thompson, Craig A. (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06835627
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming a DMOS device, and in particular, to a method for forming a body region in a drain region of the DMOS device appropriately aligned in the DMOS device. The invention also relates to a DMOS device.
BACKGROUND TO THE INVENTION
Power integrated circuits in many cases require a combination of lateral DMOS (LDMOS) devices and CMOS devices as well as bipolar CMOS (SiCMOS) devices on the same chip. Indeed, there are many other types of integrated circuits where it is desirable to provide a combination of DMOS and CMOS and/or BiCMOS devices on the same chip. From here on the term “CMOS process” is intended to cover both CMOS and BiCMOS processes. However, known processes for forming DMOS devices are different to known processes for forming CMOS devices, and thus, in general, where it is desired to produce a wafer comprising chips having combinations of DMOS and CMOS devices, the wafer must be subjected to both CMOS and DMOS forming processes. This adds considerably to both the production time and cost of producing such chips with combinations of CMOS and DMOS devices. In the manufacture of DMOS devices, and in particular, LDMOS devices it is essential that a body region which is to be formed in the drain region of the LDMOS device should extend partly beneath the gate of the device, and furthermore, should appropriately aligned with the gate of LDMOS device,
In a paper entitled “LDMOS Implementation by Large Tilt Implant in 0.6 &mgr;m BCD5 Process. Flash Memory Compatible” read at the International Symposium of Power Semiconductor Devices, May 1996, and published with the proceedings of the Symposium, Contiero, et al of SGS-Thompson Microelectronics disclose a method for integrating a self-aligned lateral DNMOS (LDNMOS) device into a bipolar CMOS, DMOS process. In this process the LDNMOS device is fabricated up to and including the gate using a CMOS process. The P-body region is then formed beneath the gate by implanting an appropriate dopant into the drain region at an angle to the surface of the drain region using an edge of the gate to form part of the mask on the drain region which defines the area of the surface of the drain region through which the dopant is to be implanted. The dopant is directed in a direction towards the drain region and the edge of the gate for implanting the dopant partly under the gate. In other words, the dopant is implanted using a single large angle of tilt from a perpendicular axis extending from the general plane of a wafer on which the device is being formed. Subsequent to implanting the dopant is diffused into a portion of the drain region for forming the P-body using a suitable CMOS diffusion process. Contiero, et al disclose three possible tilt angles, namely, 30°, 40° and 60°, from which the single tilt angle may be selected. A 45° dopant implant tilt angle appears from the paper of Contiero, et al to be the optimum.
While in the method of Contiero, et al the P-body extends beneath the gate, and is appropriately aligned therewith, the LDNMOS of Contiero, et al suffers from a number of disadvantages. In particular, it is difficult using the method of Contiero, et al to determine the breakdown voltage from source to drain in a lateral or a vertical direction due to punchthrough independently of the drain/source threshold voltage in the LDMOS for a particular well doping concentration, and vice versa. In order to achieve a desirably low drain/source threshold voltage the dose and energy level of the dopant required are such as to result in a relatively low punchthrough breakdown voltage, while on the other hand if the dopant dosage and energy level is set to achieve a relatively high punchthrough breakdown voltage the drain/source threshold voltage is undesirably high. Similarly it is difficult using the method of Contiero, et al to determine the avalanche breakdown voltage independently of the drain/source threshold voltage in the LDMOS. Thus, while the method proposed by Contiero, et al provides for the forming of an LDNMOS device using a CMOS process, the LDNMOS device, in general, is unsuitable for most applications.
There is therefore a need for a method for producing a DMOS device which overcomes these problems, and in particular, a method for forming such a DMOS device using a CMOS process.
The present invention is directed towards providing such a method and a DMOS device.
SUMMARY OF THE INVENTION
According to the invention there is provided a method for forming a body region in a drain region of a DMOS device on a wafer after the gate has been formed with the body region extending partly beneath a gate of the DMOS device and appropriately aligned with the gate, the drain region defining a surface plane, the method comprising the steps of:
(a) implanting a suitable dopant in a portion of the drain region adjacent the gate for forming the body region to have a desired drain/source threshold voltage, and
(b) implanting a suitable dopant in the said portion of the drain region adjacent the gate for forming the body region to have a desired breakdown voltage through the drain region,
steps (a) and (b) being performed in any order, and the dopant being implanted in step (a) by directing the dopant at a first angle to the surface plane of the drain region for directing at least some of the dopant beneath the gate, the first angle to the surface plane at which the dopant is directed in step (a) being less than a second angle to the surface plane at which the dopant is directed in step (b).
Preferably, the dopant is directed at the first angle towards the surface plane in step (a) in a general source/drain direction. Advantageously, the dopant is directed at the second angle towards the surface plane in step (b) in a general source/drain direction.
In one embodiment of the invention the first angle to the surface plane of the drain region at which the dopant is directed in step (a) lies in the range of 30° to 60°. Preferably, the first angle to the surface plane of the drain region at which the dopant is directed in step (a) lies in the range of 40° to 50°. Advantageously, the first angle to the surface plane of the drain region at which the dopant is directed in step (a) is approximately 45°.
In another embodiment of the invention the second angle to the surface plane of the drain region at which the dopant is directed in step (b) lies in the range of 70° to 90°. Preferably, the second angle to the surface plane of the drain region at which the dopant is directed in step (b) lies in the range of 78° to 88°. Advantageously, the second angle to the surface plane of the drain region at which the dopant is directed in step (b) is approximately 83°.
In one embodiment of the invention the dopant is implanted in the drain region in each of steps (a) and (b) using an edge of the gate adjacent the source as part of a mask for defining a portion of the surface of the drain region through which the dopant is to be implanted. The dopant implanted in each of steps (a) and (b) may be the same or different, and the dopant implanted in each of steps (a) and (b) may be implanted at the same or different dose and/or energy levels.
In one embodiment of the invention the dopant implanted in the drain region in each of steps (a) and (b) is diffused by a dopant diffusion process for forming the body region. Alternatively, the dopant implanted in the drain region in each of the steps (a) and (b) is diffused in the drain region before the dopant of the next of the steps (a) and (b) is implanted.
In one embodiment of the invention step (a) is carried out before step (b).
In another embodiment of the invention the drain region is formed by an N-well, and the body region is formed as a P-body, and the dopant of each of steps (a) and (b) is boron.
In a further embodiment of the invention the drain region is formed by a P-well, and the body region is an N-body, and the dopant of each of steps (a) and (b) is phosphorous.
Ideally, the dose and energy levels of the dopant implanted in each of steps (a) a
Bain Andrew David
Whiston Seamus Paul
Analog Devices Inc.
Thompson Craig A.
Wolf Greenfield & Sacks P.C.
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