Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-02
2001-10-02
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S246000, C438S386000, C438S389000
Reexamination Certificate
active
06297088
ABSTRACT:
RELATED APPLICATION
This application claims priority to Taiwan, R.O.C. Application No. 88118258 filed Oct. 21, 1999 which is herein incorporated by reference.
FIELD OF THE INVENTION
The present invention relates to a process for manufacturing a semiconductor device, and more specifically, to a process for manufacturing a deep trench for a Dynamic Random Access Memory (DRAM) cell.
BACKGROUND OF THE INVENTION
With the coming of Ultra Large Scale Integrated (ULSI) DRAM devices, the sizes of memory cells have gotten smaller and smaller such that the area available for a single memory cell has become very small. This causes reduction in capacitor area, resulting in the reduction of cell capacitance. Accordingly, for the memory cells in DRAM devices, the most important issue currently is how to promote the storage ability and operation stability of capacitors when the scales of devices still decreases and the integration increases. Thus, the susceptibility of capacitors due to &agr; particle radiation and soft errors is lowered, and the increasing refresh frequency is improved.
For solving the issues above, the prior art approaches to overcome these problems have resulted in the development of the various types of capacitors, such as the trench capacitor and the stacked capacitor. However, the manufacture of the stacked capacitor causes difficulties due to the limitation of the lithography technique. Besides, enormous stacked structures for promoting storage capacity usually cause the crack of the stacked structure occurring due to the unequally stress. On the other hand, the storing capacity of trench capacitor can not be promoted effectively due to the scale of trench capacitor is restricted. In additional, the tunneling leakage is also an important issue for manufacturing the trench capacitors with the scale of trench capacitor smaller than micrometer.
In general, the structure of the typical trench capacitors is illustrated in FIG.
1
. First, the trench structures are formed in the substrate
2
by performing the etching step. Then, the doped areas
14
which acts as the first electrodes of the capacitors are formed in the lower sidewalls and bottoms of the trench structures in the substrate
2
by performing the impurity diffusion procedure. Next, the first conducting layer
18
, the second conducting layer
22
and the amorphous layer
24
are formed in the trench structures to serve as the second electrodes of the trench capacitors. The capacitor dielectric films
16
are formed between the first conducting layer
18
and the doped areas
14
above for serving as a dielectric layer of the capacitor. Similarly, the collar oxide layer
20
is used to separate the second conducting layer
22
from the substrate
2
. Besides, the amorphous layer
24
is electrically connected to the source/drain areas
30
of the transistor
28
to perform the required operation. And the shallow trench insulators (STI)
26
are formed on the amorphous layer
24
to separate the amorphous layer
24
and transistor devices
28
.
It is noted that the second conducting layer
22
, the drains of the transistor devices
28
and buried N-well
33
, as shown in
FIG. 1
, constitute a vertical transistor. The second conducting layer
22
acts as the gate of the vertical transistor, and the drains
30
and the buried N-well
33
are used to serve as the source/drain areas of the vertical transistor respectively. And the collar oxide layer
20
acts as a gate oxide. Referring to
FIG. 1
, wherein a portion of the upper sidewalls of the trenches acts as the channel of the vertical transistor. But in actual operation, the collar oxide layer
20
is maintained at a consistent value to prevent the leakage currents ascribed to the vertical device. Especially the leakage current issues are more frequently because the potential level of the second conducting layer
22
for serving as the gate of the vertical transistor is higher through the transistors
28
to a higher voltage V
cc
. Thus for solving the leakage issues, the length of the collar oxide layer
20
is maintained to prevent forming the channels of the vertical devices for reducing the current leakage. Namely, the length of collar oxide layer
20
must be bigger than the predetermined limitation for defining the channel of the vertical transistor.
However, due to the length of the collar oxide layer
20
is limited by the design rules of the process window resulting that the trenches with higher aspect ratio can't used for the capacitors, the methods of increasing the depth of the trench structures are used to increase the surface areas of the doped areas
14
and to increase the capacitance. But with the increasing integration, the sizes of the trench structures are reduced mainly, and that causes the much difficulty happen in etching the trench to a enough predetermined depth, depositing the films and contacting layers into the trench structures for defining the various devices.
SUMMARY OF THE INVENTION
The prime objective of the present invention is to provide a method for manufacturing a deep trench capacitor for a DRAM cell.
The second objective of the present invention is to provide a method for enlarge the surface of the deep trench capacitor of the DRAM cell to a portion of the collar oxide layer.
The another objective of the present invention is to provide a method for increasing the surface of the trench capacitor by using the selectively etching methods for forming the bottle-shaped trench capacitor.
The further objective of the present invention is to increase the sruface of the trench capacitor by forming the amorphous films with the hemi-spherical grained (HSG) surface.
A method of forming a DRAM cell with a trench capacitor over a semiconductor substrate comprises the following steps. First an etching step is performed to form a trench structure in the substrate, wherein the trench structure has a bottom and sidewalls, and each sidewall includes an upper sidewall adjacent to the substrate through the insulating layer and a lower sidewall adjacent to the substrate through the dielectric layer. Next a first oxide layer is filled into the trench structure by using the CVD methods. And a blanket etchback step is performed to define the upper sidewalls of the trenchs. Subsequently a silicon oxide layer is formed on the upper sidewall by performing the thermal oxidation procedure. And silicon nitride layer is formed on the silicon oxide layer. After performing an isotropically etching to the silicon nitride layer, the collar structures are formed. Then, the first oxide layer is removed by using the HF solution for wet etching. A doped area is next formed on the bottom and the lower sidewall by performing the ion diffusion step for serving as the first electrode. A doped amorphous silicon (a-silicon) film is formed on the doped area and partial the collar nitride spacers. A second oxide layer is deposited to fill into the trench structure to define the areas which the doped a-silicon film covers the collar silicon nitride layer by performing an etching back procedure. The portion of doped a-silicon film exposed by the second silicon oxide layer is removed by HNO
3
+HF solutions. Next the second silicon oxide layer is removed. A dielectric layer is next formed on the residual doped a-silicon film and a portion of the collar silicon nitride layer. And a conducting layer is filled into the trench structure for serving as the second storage electrode. Then, again the HNO
3
+HF solution is used to etchback for the whole silicon materials for exposing the capacitor contacing layer defined in latter steps and the buried strap of the transistor devices. Before depositing the a-silicon layer for the buried strap, the H
3
PO
4
at a higher temperature and HF solution are used to remove the collar silicon nitride layer and the thermal oxide layer in the BS area, then the a-silicon is deposited and etchback. A gate structure and active areas are formed above the substrate, and the drain/source (D/S) structures are formed adjacent to the gat
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