Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-01-12
1998-10-13
Tsai, Jey
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438254, H01L 218242
Patent
active
058211411
ABSTRACT:
The invention provides a method of manufacturing a cylindrical capacitor for a DRAM that has a pin shaped plug 42 that increases the photo alignment tolerances between a pin plug 42 and a cylindrical top crown 50A. The invention provides a capacitor structure with a pin shaped plug hole 40 (40A 40B) that has a wide upper hemispherical plug hole 40B and a narrower cylindrical lower plug hole 40A. There are two embodiments to forming the pin plug hole 40. In the first embodiment, (1) an isotropic etch forms the wide upper hemispherical plug hole 40B followed by, (2) an anisotropic etch forms the narrower cylindrical lower plug hole 40B. In the second embodiment, the first insulating layer 30 is composed of an upper layer 30B (with a fast wet etch rate) and a lower layer 30A (with a slow wet etch rate). Then the layer 30 is etched by a wet and a dry etch (in either order) to form the pin plug opening 30.
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Ackerman Stephen B.
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company Ltd
Tsai Jey
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